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soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL

This commit is contained in:
Florent Kermarrec 2020-02-18 10:15:01 +01:00
parent 9baa3ad5bb
commit ae45be4773
1 changed files with 4 additions and 4 deletions
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8
litex/soc/cores/clock.py
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@ -292,8 +292,8 @@ class S7MMCM(XilinxClocking):
class S7IDELAYCTRL(Module): class S7IDELAYCTRL(Module):
def __init__(self, cd): def __init__(self, cd, reset_cycles=16):
reset_counter = Signal(4, reset=15) reset_counter = Signal(log2_int(reset_cycles), reset=reset_cycles - 1)
ic_reset = Signal(reset=1) ic_reset = Signal(reset=1)
sync = getattr(self.sync, cd.name) sync = getattr(self.sync, cd.name)
sync += \ sync += \
@ -385,8 +385,8 @@ class USMMCM(XilinxClocking):
class USIDELAYCTRL(Module): class USIDELAYCTRL(Module):
def __init__(self, cd): def __init__(self, cd, reset_cycles=64):
reset_counter = Signal(6, reset=63) reset_counter = Signal(log2_int(reset_cycles), reset=reset_cycles - 1)
ic_reset = Signal(reset=1) ic_reset = Signal(reset=1)
sync = getattr(self.sync, cd.name) sync = getattr(self.sync, cd.name)
sync += \ sync += \