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jtag/jtagbone: Expose chain parameter.

This commit is contained in:
Florent Kermarrec 2021-05-06 14:58:47 +02:00
parent 3ce5f3867a
commit aea1e7fb20
2 changed files with 6 additions and 6 deletions
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8
litex/soc/cores/jtag.py
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@ -88,7 +88,7 @@ class USJTAG(XilinxJTAG):
# JTAG PHY ----------------------------------------------------------------------------------------- # JTAG PHY -----------------------------------------------------------------------------------------
class JTAGPHY(Module): class JTAGPHY(Module):
def __init__(self, jtag=None, device=None, data_width=8, clock_domain="sys"): def __init__(self, jtag=None, device=None, data_width=8, clock_domain="sys", chain=1):
"""JTAG PHY """JTAG PHY
Provides a simple JTAG to LiteX stream module to easily stream data to/from the FPGA Provides a simple JTAG to LiteX stream module to easily stream data to/from the FPGA
@ -118,11 +118,11 @@ class JTAGPHY(Module):
# JTAG TAP --------------------------------------------------------------------------------- # JTAG TAP ---------------------------------------------------------------------------------
if jtag is None: if jtag is None:
if device[:3] == "xc6": if device[:3] == "xc6":
jtag = S6JTAG() jtag = S6JTAG(chain=chain)
elif device[:3] == "xc7": elif device[:3] == "xc7":
jtag = S7JTAG() jtag = S7JTAG(chain=chain)
elif device[:4] in ["xcku", "xcvu"]: elif device[:4] in ["xcku", "xcvu"]:
jtag = USJTAG() jtag = USJTAG(chain=chain)
else: else:
raise NotImplementedError raise NotImplementedError
self.submodules.jtag = jtag self.submodules.jtag = jtag

4
litex/soc/integration/soc.py
View File

@ -1203,11 +1203,11 @@ class LiteXSoC(SoC):
self.bus.add_master(name="uartbone", master=self.uartbone.wishbone) self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
# Add JTAGbone --------------------------------------------------------------------------------- # Add JTAGbone ---------------------------------------------------------------------------------
def add_jtagbone(self): def add_jtagbone(self, chain=1):
from litex.soc.cores import uart from litex.soc.cores import uart
from litex.soc.cores.jtag import JTAGPHY from litex.soc.cores.jtag import JTAGPHY
self.check_if_exists("jtabone") self.check_if_exists("jtabone")
self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device) self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain)
self.submodules.jtagbone = uart.UARTBone(phy=self.jtagbone_phy, clk_freq=self.sys_clk_freq) self.submodules.jtagbone = uart.UARTBone(phy=self.jtagbone_phy, clk_freq=self.sys_clk_freq)
self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone) self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone)