setup: add litex_json2dts to console_scripts.
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@ -176,7 +176,7 @@ def generate_dts(d):
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for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
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for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
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if name in d["csr_bases"]:
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if name in d["csr_bases"]:
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dts += """
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dts += """
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{pwm_name}: pwm@{pwm_csr_base:x} {{
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{pwm_name}: pwm@{pwm_csr_base:x} {{
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compatible = "litex,pwm";
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compatible = "litex,pwm";
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@ -357,7 +357,7 @@ def generate_dts(d):
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# ICAPBitstream ------------------------------------------------------------------------------------
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# ICAPBitstream ------------------------------------------------------------------------------------
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if "icap_bit" in d["csr_bases"]:
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if "icap_bit" in d["csr_bases"]:
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dts += """
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dts += """
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fpga0: icap@{icap_csr_base:x} {{
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fpga0: icap@{icap_csr_base:x} {{
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compatible = "litex,fpga-icap";
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compatible = "litex,fpga-icap";
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@ -448,7 +448,7 @@ def generate_dts(d):
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};"""
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};"""
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# SDCARD -------------------------------------------------------------------------------------------
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# SDCARD -------------------------------------------------------------------------------------------
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if "sdcore" in d["csr_bases"]:
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if "sdcore" in d["csr_bases"]:
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dts += """
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dts += """
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@ -510,8 +510,7 @@ def generate_dts(d):
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return dts
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return dts
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if __name__ == "__main__":
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def main():
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parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
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parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
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parser.add_argument("csr_json", help="CSR JSON file")
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parser.add_argument("csr_json", help="CSR JSON file")
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args = parser.parse_args()
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args = parser.parse_args()
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@ -519,3 +518,7 @@ if __name__ == "__main__":
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d = json.load(open(args.csr_json))
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d = json.load(open(args.csr_json))
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print(generate_dts(d))
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print(generate_dts(d))
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if __name__ == "__main__":
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main()
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1
setup.py
1
setup.py
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@ -43,6 +43,7 @@ setup(
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"litex_sim=litex.tools.litex_sim:main",
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"litex_sim=litex.tools.litex_sim:main",
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"litex_read_verilog=litex.tools.litex_read_verilog:main",
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"litex_read_verilog=litex.tools.litex_read_verilog:main",
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"litex_simple=litex.boards.targets.simple:main",
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"litex_simple=litex.boards.targets.simple:main",
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"litex_json2dts=litex.tools.litex_json2dts:main",
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# short names
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# short names
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"lxterm=litex.tools.litex_term:main",
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"lxterm=litex.tools.litex_term:main",
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"lxserver=litex.tools.litex_server:main",
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"lxserver=litex.tools.litex_server:main",
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