Update README.md and core.py for BlackParrot
This commit is contained in:
sadullah
parent
5e4a436089
commit
aed1d514ab
|
|
@ -1,24 +0,0 @@
|
|||
# Getting started (TODO:update)
|
||||
|
||||
## Running BP in LiteX
|
||||
|
||||
cd $LITEX/litex/tools # the folder where litex simulator resides
|
||||
|
||||
./litex_sim.py --cpu-type blackparrot --cpu-variant standard --integrated-rom-size 40960 --output-dir build/BP --threads 4 --opt-level=O0 --trace --trace-start 0
|
||||
|
||||
#The above command will generate a dut.vcd file under build/BP/gateware folder. gtkwave works fine with the generated dut.vcd.
|
||||
|
||||
## Additional Information
|
||||
|
||||
The BlackParrot resides in $BP/pre-alpha-release/
|
||||
|
||||
core.py in $BP folder is the wrapper that integrates BP into LiteX.
|
||||
|
||||
flist.verilator in $BP is all the files that litex_sim fetches for simulation.
|
||||
|
||||
The top module is $BP_FPGA_DIR/ExampleBlackParrotSystem.v
|
||||
|
||||
The transducer for wishbone communication is $BP_FPGA_DIR/bp2wb_convertor.v
|
||||
|
||||
if args.sdram_init is not None: #instead of ram_init for sdram init boot
|
||||
soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
|
||||
|
|
@ -1,60 +1,41 @@
|
|||
# BlackParrot in LiteX
|
||||
|
||||
|
||||
## Getting Started
|
||||
## Prerequisites and Installing
|
||||
|
||||
TODO: modify getting started [Getting Started (Full)](GETTING_STARTED.md)
|
||||
Please visit https://github.com/scanakci/linux-on-litex-blackparrot for the detailed setup instructions and linux boot-up process.
|
||||
|
||||
### Prerequisites
|
||||
## Set necessary environment variables for BlackParrot
|
||||
|
||||
Running BP in LiteX requires setting some environment variables. Please add the following lines to your bashrc to set them up.
|
||||
|
||||
```
|
||||
BP sources (https://github.com/litex-hub/pythondata-cpu-blackparrot)
|
||||
RISC-V toolchain built for IA architecture (prebuilt binaries provided by LiteX works fine)
|
||||
Verilator (tested with Verilator 4.031)
|
||||
```
|
||||
|
||||
### Installing
|
||||
|
||||
```
|
||||
https://github.com/litex-hub/pythondata-cpu-blackparrot is required to run BP in LiteX.
|
||||
source ./setEnvironment.sh #should be sourced each time you open a terminal or just add this line to bashrc
|
||||
pushd .
|
||||
cd PATH/TO/LITEX/litex/soc/cores/cpu/blackparrot
|
||||
source ./setEnvironment.sh
|
||||
popd
|
||||
```
|
||||
|
||||
## Running BIOS
|
||||
|
||||
[](https://asciinema.org/a/326077)
|
||||
|
||||
### Simulation
|
||||
```
|
||||
cd $LITEX/litex/tools
|
||||
./litex_sim.py --cpu-type blackparrot --cpu-variant standard --output-dir build/BP_Trial
|
||||
```
|
||||
[](https://asciinema.org/a/326077)
|
||||
|
||||
### FPGA
|
||||
```
|
||||
Coming soon!
|
||||
```
|
||||
|
||||
## Running Linux
|
||||
|
||||
|
||||
### Simulation
|
||||
```
|
||||
Modify litex_sim.py by replacing soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) with soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
|
||||
|
||||
./litex_sim.py --cpu-type blackparrot --cpu-variant standard --integrated-rom-size 40960 --output-dir build/BP_newversion_linux_ram/ --threads 4 --ram-init build/tests/boot.bin.uart.simu.trial
|
||||
|
||||
TODO: add prebuilt bbl files into python-data repository
|
||||
|
||||
```
|
||||
|
||||
### FPGA
|
||||
|
||||
Generate the bitstream 'top.bit' under build/BP_trial/gateware folder
|
||||
```
|
||||
Coming soon!
|
||||
$LITEX/litex/boards/genesys2.py --cpu-type blackparrot --cpu-variant standard --output-dir $PWD/build/BP_Trial --integrated-rom-size 51200 --build
|
||||
```
|
||||
In another terminal, launch LiteX terminal.
|
||||
```
|
||||
sudo $LITEX/litex/tools/litex_term.py /dev/ttyUSBX
|
||||
```
|
||||
Load the FPGA bitstream top.bit to your FPGA (you can use vivado hardware manager)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
This step will execute LiteX BIOS.
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
import os
|
||||
|
||||
import sys
|
||||
from migen import *
|
||||
|
||||
from litex import get_data_mod
|
||||
|
|
@ -108,7 +108,15 @@ class BlackParrotRV64(CPU):
|
|||
)
|
||||
|
||||
# add verilog sources
|
||||
self.add_sources(platform, variant)
|
||||
try:
|
||||
os.environ["BP"]
|
||||
os.environ["LITEX"]
|
||||
self.add_sources(platform, variant)
|
||||
except KeyError:
|
||||
RED = '\033[91m'
|
||||
print(RED + "Please set environment variables first, refer to readme file under litex/soc/cores/cpu/blackparrot for details!")
|
||||
sys.exit(1)
|
||||
|
||||
|
||||
def set_reset_address(self, reset_address):
|
||||
assert not hasattr(self, "reset_address")
|
||||
|
|
@ -137,14 +145,14 @@ class BlackParrotRV64(CPU):
|
|||
a = os.popen('echo '+ str(dir_))
|
||||
dir_start = a.read()
|
||||
vdir = dir_start[:-1] + line[s2:-1]
|
||||
platform.add_verilog_include_path(vdir) #this line might be changed
|
||||
platform.add_verilog_include_path(vdir)
|
||||
elif (temp[0]=='$') :
|
||||
s2 = line.find('/')
|
||||
dir_ = line[0:s2]
|
||||
a = os.popen('echo '+ str(dir_))
|
||||
dir_start = a.read()
|
||||
vdir = dir_start[:-1]+ line[s2:-1]
|
||||
platform.add_source(vdir, "systemverilog") #this line might be changed
|
||||
platform.add_source(vdir, "systemverilog")
|
||||
elif (temp[0] == '/'):
|
||||
assert("No support for absolute path for now")
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue