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uart: add phy autodetect function

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This commit is contained in:
Florent Kermarrec 2015-03-06 10:19:29 +01:00
parent e133777450
commit af66ca7bad
2 changed files with 14 additions and 6 deletions
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12
misoclib/com/uart/phy/__init__.py
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@ -0,0 +1,12 @@
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.uart.phy.sim import UARTPHYSim
from misoclib.com.uart.phy.serial import UARTPHYSerial
def UARTPHY(pads, *args, **kwargs):
# Autodetect PHY
if hasattr(pads, "source_stb"):
return UARTPHYSim(pads, *args, **kwargs)
else:
return UARTPHYSerial(pads, *args, **kwargs)

8
misoclib/soc/__init__.py
View file

@ -6,8 +6,7 @@ from migen.fhdl.std import *
from migen.bank import csrgen from migen.bank import csrgen
from migen.bus import wishbone, csr, wishbone2csr from migen.bus import wishbone, csr, wishbone2csr
from misoclib.com.uart.phy.serial import UARTPHYSerial from misoclib.com.uart.phy import UARTPHY
from misoclib.com.uart.phy.sim import UARTPHYSim
from misoclib.com import uart from misoclib.com import uart
from misoclib.cpu import CPU, lm32, mor1kx from misoclib.cpu import CPU, lm32, mor1kx
from misoclib.cpu.peripherals import identifier, timer from misoclib.cpu.peripherals import identifier, timer
@ -111,10 +110,7 @@ class SoC(Module):
self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone) self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
if with_uart: if with_uart:
if getattr(platform, "is_sim", False): self.submodules.uart_phy = UARTPHY(platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart_phy = UARTPHYSim(platform.request("serial"))
else:
self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy) self.submodules.uart = uart.UART(self.uart_phy)
if with_identifier: if with_identifier: