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targets: fix MiniSoC

This commit is contained in:
Florent Kermarrec 2015-02-27 17:12:37 +01:00
parent e07e124118
commit b031c5edae
2 changed files with 2 additions and 2 deletions
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2
targets/kc705.py
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@ -131,6 +131,6 @@ class MiniSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000) self.add_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000)
default_subtarget = BaseSoC default_subtarget = BaseSoC

2
targets/mlabs_video.py
View File

@ -101,7 +101,7 @@ class MiniSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000) self.add_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000)
def get_vga_dvi(platform): def get_vga_dvi(platform):
try: try: