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vexriscv/core: fix min variant

This commit is contained in:
Florent Kermarrec 2019-03-15 17:49:39 +01:00
parent a549f0941b
commit b04a756abb
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/cpu/vexriscv/core.py
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@ -155,8 +155,8 @@ class VexRiscv(Module, AutoCSR):
"std_debug": "VexRiscv_Debug.v",
"lite": "VexRiscv_Lite.v",
"lite_debug": "VexRiscv_LiteDebug.v",
"min": "VexRiscv_Lite.v",
"min_debug": "VexRiscv_LiteDebug.v",
"min": "VexRiscv_Min.v",
"min_debug": "VexRiscv_MinDebug.v",
}
cpu_filename = verilog_variants[variant]
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")