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cores/jtag: Fix chain parameter on XilinxJTAG.

This commit is contained in:
Florent Kermarrec 2022-03-03 16:45:20 +01:00
parent e00eafd97f
commit b092d2a180
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/jtag.py
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@ -401,7 +401,7 @@ class JTAGPHY(Module):
if jtag is None: if jtag is None:
# Xilinx. # Xilinx.
if XilinxJTAG.get_primitive(device) is not None: if XilinxJTAG.get_primitive(device) is not None:
jtag = XilinxJTAG(primitive=XilinxJTAG.get_primitive(device)) jtag = XilinxJTAG(primitive=XilinxJTAG.get_primitive(device), chain=chain)
# Lattice. # Lattice.
elif device[:5] == "LFE5U": elif device[:5] == "LFE5U":
jtag = ECP5JTAG() jtag = ECP5JTAG()