cores/jtag: Fix chain parameter on XilinxJTAG.

2022-03-03 16:45:20 +01:00 · 2022-03-03 16:45:20 +01:00 · b092d2a180
parent e00eafd97f
commit b092d2a180
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/jtag.py
+++ b/litex/soc/cores/jtag.py
@ -401,7 +401,7 @@ class JTAGPHY(Module):
        if jtag is None:
            # Xilinx.
            if XilinxJTAG.get_primitive(device) is not None:
-                jtag = XilinxJTAG(primitive=XilinxJTAG.get_primitive(device))
+                jtag = XilinxJTAG(primitive=XilinxJTAG.get_primitive(device), chain=chain)
            # Lattice.
            elif device[:5] == "LFE5U":
                jtag = ECP5JTAG()