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test_cpu: Add Microwatt to tested CPUs 

Now that LiteX can convert from VHDL to Verilog using GHDL, and the
required dependencies are installed in the CI environment, start testing
Microwatt.

Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Joel Stanley 2022-10-28 11:26:06 +10:30
parent f89746af9f
commit b0b57491bb
1 changed files with 1 additions and 1 deletions
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2
test/test_cpu.py
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@ -45,6 +45,7 @@ class TestCPU(unittest.TestCase):
"serv", # (riscv / softcore) "serv", # (riscv / softcore)
"vexriscv", # (riscv / softcore) "vexriscv", # (riscv / softcore)
"vexriscv_smp", # (riscv / softcore) "vexriscv_smp", # (riscv / softcore)
"microwatt", # (ppc64 / softcore)
] ]
untested_cpus = [ untested_cpus = [
"blackparrot", # (riscv / softcore) -> Broken install? "blackparrot", # (riscv / softcore) -> Broken install?
@ -57,7 +58,6 @@ class TestCPU(unittest.TestCase):
"gowin_emcu", # (arm / hardcore) -> Hardcore. "gowin_emcu", # (arm / hardcore) -> Hardcore.
"ibex", # (riscv / softcore) -> Broken since 2022.11.12. "ibex", # (riscv / softcore) -> Broken since 2022.11.12.
"lm32", # (lm32 / softcore) -> Requires LM32 toolchain. "lm32", # (lm32 / softcore) -> Requires LM32 toolchain.
"microwatt", # (ppc64 / softcore) -> Requires PPC toolchain + VHDL->Verilog (GHDL + Yosys).
"minerva", # (riscv / softcore) -> Broken install? (Amaranth?) "minerva", # (riscv / softcore) -> Broken install? (Amaranth?)
"mor1kx", # (or1k / softcore) -> Verilator compilation issue. "mor1kx", # (or1k / softcore) -> Verilator compilation issue.
"neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys). "neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys).