verilog: handle default in case statements

2011-12-08 23:04:20 +01:00 · 2011-12-08 23:04:20 +01:00 · b0c5b74c22
parent 512655c108
commit b0c5b74c22
1 changed files with 4 additions and 0 deletions
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@ -65,6 +65,10 @@ def _printnode(ns, level, comb, node):
 			r += "\t"*(level + 1) + _printexpr(ns, case[0]) + ": begin\n"
 			r += _printnode(ns, level + 2, comb, case[1])
 			r += "\t"*(level + 1) + "end\n"
+		if node.default.l:
+			r += "\t"*(level + 1) + "default: begin\n"
+			r += _printnode(ns, level + 2, comb, node.default)
+			r += "\t"*(level + 1) + "end\n"
 		r += "\t"*level + "endcase\n"
 		return r
 	else: