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Build your hardware, easily!
23 Commits 37 Branches 13 Tags 47 MiB
C 53.1%
Python 43.2%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
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Sebastien Bourdeauducq b0c5b74c22 verilog: handle default in case statements 2011-12-08 23:04:20 +01:00
examples Corelogic conversion example 2011-12-08 21:25:05 +01:00
migen verilog: handle default in case statements 2011-12-08 23:04:20 +01:00
.gitignore Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00