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verilog: handle default in case statements

This commit is contained in:
Sebastien Bourdeauducq 2011-12-08 23:04:20 +01:00
parent 512655c108
commit b0c5b74c22
1 changed files with 4 additions and 0 deletions
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4
migen/fhdl/verilog.py
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@ -65,6 +65,10 @@ def _printnode(ns, level, comb, node):
r += "\t"*(level + 1) + _printexpr(ns, case[0]) + ": begin\n" r += "\t"*(level + 1) + _printexpr(ns, case[0]) + ": begin\n"
r += _printnode(ns, level + 2, comb, case[1]) r += _printnode(ns, level + 2, comb, case[1])
r += "\t"*(level + 1) + "end\n" r += "\t"*(level + 1) + "end\n"
if node.default.l:
r += "\t"*(level + 1) + "default: begin\n"
r += _printnode(ns, level + 2, comb, node.default)
r += "\t"*(level + 1) + "end\n"
r += "\t"*level + "endcase\n" r += "\t"*level + "endcase\n"
return r return r
else: else: