use description instead of layout

lib/sata/command/__init__.py

@@ -11,7 +11,7 @@ from_rx = [
 
 class SATACommandTX(Module):
 	def __init__(self, transport):
-		self.sink = sink = Sink(command_tx_layout(32))
+		self.sink = sink = Sink(command_tx_description(32))
 		self.from_rx = Sink(from_rx)
 
 		###
@@ -109,7 +109,7 @@ class SATACommandTX(Module):
 
 class SATACommandRX(Module):
 	def __init__(self, transport):
-		self.source = source = Source(command_tx_layout(32))
+		self.source = source = Source(command_tx_description(32))
 		self.to_tx = Source(from_rx)
 
 		###

lib/sata/common.py

@@ -32,14 +32,14 @@ def decode_primitive(dword):
 			return k
 	return ""
 
-def phy_layout(dw):
+def phy_description(dw):
 	layout = [
 		("data", dw),
 		("charisk", dw//8),
 	]
 	return EndpointDescription(layout, packetized=False)
 
-def link_layout(dw):
+def link_description(dw):
 	layout = [
 		("d", dw),
 		("error", 1)
@@ -106,7 +106,7 @@ fis_data_layout = {
 	"type": FISField(0,  0, 8)
 }
 
-def transport_tx_layout(dw):
+def transport_tx_description(dw):
 	layout = [
 		("type", 8),
 		("pm_port", 4),
@@ -122,7 +122,7 @@ def transport_tx_layout(dw):
 	]
 	return EndpointDescription(layout, packetized=True)
 
-def transport_rx_layout(dw):
+def transport_rx_description(dw):
 	layout = [
 		("type", 8),
 		("pm_port", 4),
@@ -143,7 +143,7 @@ regs = {
 	"IDENTIFY_DEVICE_DMA"	: 0xEE
 }
 
-def command_tx_layout(dw):
+def command_tx_description(dw):
 	layout = [
 		("write", 1),
 		("read", 1),
@@ -154,7 +154,7 @@ def command_tx_layout(dw):
 	]
 	return EndpointDescription(layout, packetized=True)
 
-def command_rx_layout(dw):
+def command_rx_description(dw):
 	layout = [
 		("write", 1),
 		("read", 1),

lib/sata/link/__init__.py

@@ -15,7 +15,7 @@ from_rx = [
 
 class SATALinkTX(Module):
 	def __init__(self, phy):
-		self.sink = Sink(link_layout(32))
+		self.sink = Sink(link_description(32))
 		self.from_rx = Sink(from_rx)
 
 		###
@@ -24,11 +24,11 @@ class SATALinkTX(Module):
 		self.submodules += fsm
 
 		# insert CRC
-		crc = SATACRCInserter(link_layout(32))
+		crc = SATACRCInserter(link_description(32))
 		self.submodules += crc
 
 		# scramble
-		scrambler = SATAScrambler(link_layout(32))
+		scrambler = SATAScrambler(link_description(32))
 		self.submodules += scrambler
 
 		# connect CRC / scrambler
@@ -39,7 +39,7 @@ class SATALinkTX(Module):
 
 		# inserter CONT and scrambled data between
 		# CONT and next primitive
-		cont  = SATACONTInserter(phy_layout(32))
+		cont  = SATACONTInserter(phy_description(32))
 		self.submodules += cont
 
 		# datas / primitives mux
@@ -113,7 +113,7 @@ class SATALinkTX(Module):
 
 class SATALinkRX(Module):
 	def __init__(self, phy):
-		self.source = Source(link_layout(32))
+		self.source = Source(link_description(32))
 		self.to_tx = Source(from_rx)
 
 		###
@@ -122,7 +122,7 @@ class SATALinkRX(Module):
 		self.submodules += fsm
 
 		# CONT remover
-		cont = SATACONTRemover(phy_layout(32))
+		cont = SATACONTRemover(phy_description(32))
 		self.submodules += cont
 		self.comb += Record.connect(phy.source, cont.sink)
 
@@ -135,11 +135,11 @@ class SATALinkRX(Module):
 			)
 
 		# descrambler
-		scrambler = SATAScrambler(link_layout(32))
+		scrambler = SATAScrambler(link_description(32))
 		self.submodules += scrambler
 
 		# check CRC
-		crc = SATACRCChecker(link_layout(32))
+		crc = SATACRCChecker(link_description(32))
 		self.submodules += crc
 
 		sop = Signal()
@@ -151,7 +151,7 @@ class SATALinkRX(Module):
 			)
 
 		# small fifo to manage HOLD
-		self.submodules.fifo = SyncFIFO(link_layout(32), 32)
+		self.submodules.fifo = SyncFIFO(link_description(32), 32)
 
 		# graph
 		self.sync += \

lib/sata/link/cont.py

@@ -5,9 +5,9 @@ from lib.sata.common import *
 from lib.sata.link.scrambler import Scrambler
 
 class SATACONTInserter(Module):
-	def __init__(self, layout):
-		self.sink = sink = Sink(layout)
-		self.source = source = Source(layout)
+	def __init__(self, description):
+		self.sink = sink = Sink(description)
+		self.source = source = Source(description)
 
 		###
 
@@ -80,9 +80,9 @@ class SATACONTInserter(Module):
 		]
 
 class SATACONTRemover(Module):
-	def __init__(self, layout):
-		self.sink = sink = Sink(layout)
-		self.source = source = Source(layout)
+	def __init__(self, description):
+		self.sink = sink = Sink(description)
+		self.source = source = Source(description)
 
 		###
 

lib/sata/link/crc.py

@@ -108,9 +108,9 @@ class SATACRC(Module):
 		]
 
 class SATACRCInserter(CRCInserter):
-	def __init__(self, layout):
-		CRCInserter.__init__(self, SATACRC, layout)
+	def __init__(self, description):
+		CRCInserter.__init__(self, SATACRC, description)
 
 class SATACRCChecker(CRCChecker):
-	def __init__(self, layout):
-		CRCChecker.__init__(self, SATACRC, layout)
+	def __init__(self, description):
+		CRCChecker.__init__(self, SATACRC, description)

lib/sata/link/scrambler.py

@@ -69,9 +69,9 @@ class Scrambler(Module):
 
 @DecorateModule(InsertReset)
 class SATAScrambler(Module):
-	def __init__(self, layout):
-		self.sink = sink = Sink(layout)
-		self.source = source = Source(layout)
+	def __init__(self, description):
+		self.sink = sink = Sink(description)
+		self.source = source = Source(description)
 
 		###
 

lib/sata/test/bfm.py

@@ -13,7 +13,7 @@ class PHYDword:
 
 class PHYSource(Module):
 	def __init__(self):
-		self.source = Source(phy_layout(32))
+		self.source = Source(phy_description(32))
 		###
 		self.dword = PHYDword()
 
@@ -30,7 +30,7 @@ class PHYSource(Module):
 
 class PHYSink(Module):
 	def __init__(self):
-		self.sink = Sink(phy_layout(32))
+		self.sink = Sink(phy_description(32))
 		###
 		self.dword = PHYDword()
 
@@ -263,22 +263,22 @@ def get_field_data(field, packet):
 	return (packet[field.dword] >> field.offset) & (2**field.width-1)
 
 class FIS:
-	def __init__(self, packet, layout):
+	def __init__(self, packet, description):
 		self.packet = packet
-		self.layout = layout
+		self.description = description
 		self.decode()
 
 	def decode(self):
-		for k, v in self.layout.items():
+		for k, v in self.description.items():
 			setattr(self, k, get_field_data(v, self.packet))
 
 	def encode(self):
-		for k, v in self.layout.items():
+		for k, v in self.description.items():
 			self.packet[v.dword] |= (getattr(self, k) << v.offset)
 
 	def __repr__(self):
 		r = "--------\n"
-		for k in sorted(self.layout.keys()):
+		for k in sorted(self.description.keys()):
 			r += k + " : 0x%x" %getattr(self,k) + "\n"
 		return r
 

lib/sata/test/link_tb.py

@@ -12,7 +12,7 @@ from lib.sata.test.common import *
 
 class LinkStreamer(Module):
 	def __init__(self):
-		self.source = Source(link_layout(32))
+		self.source = Source(link_description(32))
 		###
 		self.packets = []
 		self.packet = LinkTXPacket()
@@ -44,7 +44,7 @@ class LinkStreamer(Module):
 
 class LinkLogger(Module):
 	def __init__(self):
-		self.sink = Sink(link_layout(32))
+		self.sink = Sink(link_description(32))
 		###
 		self.packet = LinkRXPacket()
 
@@ -70,10 +70,10 @@ class TB(Module):
 		self.submodules.link = SATALink(self.bfm.phy)
 
 		self.submodules.streamer = LinkStreamer()
-		streamer_ack_randomizer = AckRandomizer(link_layout(32), level=50)
+		streamer_ack_randomizer = AckRandomizer(link_description(32), level=50)
 		self.submodules += streamer_ack_randomizer
 		self.submodules.logger = LinkLogger()
-		logger_ack_randomizer = AckRandomizer(link_layout(32), level=50)
+		logger_ack_randomizer = AckRandomizer(link_description(32), level=50)
 		self.submodules += logger_ack_randomizer
 		self.comb += [
 			Record.connect(self.streamer.source, streamer_ack_randomizer.sink),

lib/sata/transport/__init__.py

@@ -3,9 +3,9 @@ from migen.genlib.fsm import FSM, NextState
 
 from lib.sata.common import *
 
-def _encode_cmd(obj, layout, signal):
+def _encode_cmd(obj, description, signal):
 	r = []
-	for k, v in sorted(layout.items()):
+	for k, v in sorted(description.items()):
 		start = v.dword*32 + v.offset
 		end = start + v.width
 		if "_lsb" in k:
@@ -19,7 +19,7 @@ def _encode_cmd(obj, layout, signal):
 
 class SATATransportTX(Module):
 	def __init__(self, link):
-		self.sink = sink = Sink(transport_tx_layout(32))
+		self.sink = sink = Sink(transport_tx_description(32))
 
 		###
 
@@ -109,9 +109,9 @@ class SATATransportTX(Module):
 				cnt.eq(cnt+1)
 			)
 
-def _decode_cmd(signal, layout, obj):
+def _decode_cmd(signal, description, obj):
 	r = []
-	for k, v in sorted(layout.items()):
+	for k, v in sorted(description.items()):
 		start = v.dword*32+v.offset
 		end = start+v.width
 		if "_lsb" in k:
@@ -125,7 +125,7 @@ def _decode_cmd(signal, layout, obj):
 
 class SATATransportRX(Module):
 	def __init__(self, link):
-		self.source = source = Source(transport_rx_layout(32))
+		self.source = source = Source(transport_rx_description(32))
 
 		###