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litepcie/frontend/dma: add loop counter (useful to detect missed interrupts)

This commit is contained in:
Florent Kermarrec 2015-07-22 22:55:11 +02:00
parent dfc207aacb
commit b1ea3340f3
1 changed files with 6 additions and 2 deletions
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8
misoclib/com/litepcie/frontend/dma/common.py
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@ -30,6 +30,7 @@ class DMARequestTable(Module, AutoCSR):
self._loop_prog_n = CSRStorage() self._loop_prog_n = CSRStorage()
self._index = CSRStatus(log2_int(depth)) self._index = CSRStatus(log2_int(depth))
self._level = CSRStatus(log2_int(depth)) self._level = CSRStatus(log2_int(depth))
self._loop = CSRStatus(16)
self._flush = CSR() self._flush = CSR()
self.irq = Signal() self.irq = Signal()
@ -41,6 +42,7 @@ class DMARequestTable(Module, AutoCSR):
we = self._we.r & self._we.re we = self._we.r & self._we.re
loop_prog_n = self._loop_prog_n.storage loop_prog_n = self._loop_prog_n.storage
index = self._index.status index = self._index.status
loop = self._loop.status
level = self._level.status level = self._level.status
flush = self._flush.r & self._flush.re flush = self._flush.r & self._flush.re
@ -86,10 +88,12 @@ class DMARequestTable(Module, AutoCSR):
# "loop" mode # "loop" mode
self.sync += \ self.sync += \
If(flush, If(flush,
index.eq(0) index.eq(0),
loop.eq(0),
).Elif(source.stb & source.ack, ).Elif(source.stb & source.ack,
If(fifo.dout.start, If(fifo.dout.start,
index.eq(0) index.eq(0),
loop.eq(loop+1)
).Else( ).Else(
index.eq(index+1) index.eq(index+1)
) )