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soc/add_pcie: Add with_ptm parameter and update CHANGES.

This commit is contained in:
Florent Kermarrec 2023-07-30 15:12:01 +02:00
parent ff67781f11
commit b2e4b22145
2 changed files with 4 additions and 1 deletions
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1
CHANGES.md
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@ -51,6 +51,7 @@
- liteeth_gen : Added raw UDP port support. - liteeth_gen : Added raw UDP port support.
- build/vivado : Added .dcp generation also after synthesis and placement. - build/vivado : Added .dcp generation also after synthesis and placement.
- gen: : Added initial LiteXContext to easily get build properties (platform, device, toolchain, etc...) - gen: : Added initial LiteXContext to easily get build properties (platform, device, toolchain, etc...)
- litepcie/endpoint/tlp : Added optional Configuration/PTM TLP support to Packetizer/Depacketizer.
[> Changed [> Changed
---------- ----------

4
litex/soc/integration/soc.py
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@ -2001,6 +2001,7 @@ class LiteXSoC(SoC):
with_dma_monitor = False, with_dma_monitor = False,
with_dma_status = False, with_dma_status = False,
with_msi = True, msi_type="msi", msi_width=32, with_msi = True, msi_type="msi", msi_width=32,
with_ptm = False,
): ):
# Imports # Imports
from litepcie.phy.uspciephy import USPCIEPHY from litepcie.phy.uspciephy import USPCIEPHY
@ -2017,7 +2018,8 @@ class LiteXSoC(SoC):
endpoint = LitePCIeEndpoint(phy, endpoint = LitePCIeEndpoint(phy,
max_pending_requests = max_pending_requests, max_pending_requests = max_pending_requests,
endianness = phy.endianness, endianness = phy.endianness,
address_width = address_width address_width = address_width,
with_ptm = with_ptm,
) )
self.add_module(name=f"{name}_endpoint", module=endpoint) self.add_module(name=f"{name}_endpoint", module=endpoint)