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targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)

This commit is contained in:
Florent Kermarrec 2015-03-17 01:07:44 +01:00
parent faf185d58d
commit b2f32ad124
1 changed files with 2 additions and 0 deletions
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2
targets/simple.py
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@ -1,5 +1,6 @@
from migen.fhdl.std import * from migen.fhdl.std import *
from migen.bus import wishbone from migen.bus import wishbone
from migen.genlib.io import CRG
from misoclib.soc import SoC, mem_decoder from misoclib.soc import SoC, mem_decoder
from misoclib.com.liteeth.phy import LiteEthPHY from misoclib.com.liteeth.phy import LiteEthPHY
@ -12,6 +13,7 @@ class BaseSoC(SoC):
with_rom=True, with_rom=True,
with_main_ram=True, main_ram_size=16*1024, with_main_ram=True, main_ram_size=16*1024,
**kwargs) **kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
class MiniSoC(BaseSoC): class MiniSoC(BaseSoC):
csr_map = { csr_map = {