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gen/fhdl/verilog: Make DummyAttrTranslate a dict.

This commit is contained in:
Florent Kermarrec 2021-07-15 16:48:24 +02:00
parent bf52c1083f
commit b2f8fa5464
1 changed files with 1 additions and 1 deletions
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2
litex/gen/fhdl/verilog.py
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@ -369,7 +369,7 @@ def _printspecials(overrides, specials, ns, add_data_file, attr_translate):
return r return r
class DummyAttrTranslate: class DummyAttrTranslate(dict):
def __getitem__(self, k): def __getitem__(self, k):
return (k, "true") return (k, "true")