Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

test_cpu: Add NeoRV32 to tested CPUs 

With CI supporting GHDL to convert VHDL to Verilog the neorv32
simulation can be tested.

Fixes https://github.com/enjoy-digital/litex/issues/1320

Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Joel Stanley 2022-11-21 14:32:51 +10:30
parent 6b4696e3e0
commit b30dd0b5c6
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
test/test_cpu.py
View File

@ -42,6 +42,7 @@ class TestCPU(unittest.TestCase):
"firev", # (riscv / softcore) "firev", # (riscv / softcore)
"marocchino", # (or1k / softcore) "marocchino", # (or1k / softcore)
"naxriscv", # (riscv / softcore) "naxriscv", # (riscv / softcore)
"neorv32", # (riscv / softcore)
"serv", # (riscv / softcore) "serv", # (riscv / softcore)
"vexriscv", # (riscv / softcore) "vexriscv", # (riscv / softcore)
"vexriscv_smp", # (riscv / softcore) "vexriscv_smp", # (riscv / softcore)
@ -60,7 +61,6 @@ class TestCPU(unittest.TestCase):
"lm32", # (lm32 / softcore) -> Requires LM32 toolchain. "lm32", # (lm32 / softcore) -> Requires LM32 toolchain.
"minerva", # (riscv / softcore) -> Broken install? (Amaranth?) "minerva", # (riscv / softcore) -> Broken install? (Amaranth?)
"mor1kx", # (or1k / softcore) -> Verilator compilation issue. "mor1kx", # (or1k / softcore) -> Verilator compilation issue.
"neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys).
"picorv32", # (riscv / softcore) -> Verilator compilation issue. "picorv32", # (riscv / softcore) -> Verilator compilation issue.
"rocket", # (riscv / softcore) -> Not enough RAM in CI. "rocket", # (riscv / softcore) -> Not enough RAM in CI.
"zynq7000", # (arm / hardcore) -> Hardcore. "zynq7000", # (arm / hardcore) -> Hardcore.