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sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)

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This commit is contained in:
Florent Kermarrec 2015-03-29 12:34:40 +02:00
parent be20fbabe4
commit b313772a0c
2 changed files with 3 additions and 4 deletions
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3
misoclib/mem/sdram/core/lasmicon/__init__.py
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@ -9,14 +9,13 @@ from misoclib.mem.sdram.core.lasmicon.multiplexer import *
class LASMIconSettings:
def __init__(self, req_queue_size=8,
read_time=32, write_time=16,
with_l2=True, l2_size=8192,
l2_size=8192,
with_bandwidth=False,
with_memtest=False,
with_refresh=True):
self.req_queue_size = req_queue_size
self.read_time = read_time
self.write_time = write_time
self.with_l2 = with_l2
self.l2_size = l2_size
if with_memtest:
self.with_bandwidth = True

4
misoclib/soc/sdram.py
View file

@ -53,8 +53,8 @@ class SDRAMSoC(SoC):
self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
if self.sdram_controller_settings.with_l2:
l2_size = self.sdram_controller_settings.l2_size
l2_size = self.sdram_controller_settings.l2_size
if l2_size != 0:
# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
# Remove this workaround when fixed by Xilinx.