interconnect/axi: Do not expose dest on AXI-Full (Only present for on AXI-Stream).
We are using AXI-Stream for AXI-Full channels, so do an exception for dest signal.
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@ -72,6 +72,8 @@ def connect_to_pads(bus, pads, mode="master", axi_full=False):
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if channel in ["w", "r"] and axi_full:
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if channel in ["w", "r"] and axi_full:
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sig_list += [("last", 1)]
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sig_list += [("last", 1)]
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for name, width in sig_list:
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for name, width in sig_list:
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if (name == "dest"):
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continue # No DEST.
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if (channel == "w") and (name == "id") and (bus.version == "axi4"):
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if (channel == "w") and (name == "id") and (bus.version == "axi4"):
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continue # No WID on AXI4.
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continue # No WID on AXI4.
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sig = getattr(ch, name)
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sig = getattr(ch, name)
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@ -120,6 +120,8 @@ class AXIInterface:
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channel_layout = (getattr(self, channel).description.payload_layout +
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channel_layout = (getattr(self, channel).description.payload_layout +
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getattr(self, channel).description.param_layout)
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getattr(self, channel).description.param_layout)
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for name, width in channel_layout:
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for name, width in channel_layout:
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if (name == "dest"):
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continue # No DEST.
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if (channel == "w") and (name == "id") and (self.version == "axi4"):
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if (channel == "w") and (name == "id") and (self.version == "axi4"):
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continue # No WID on AXI4.
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continue # No WID on AXI4.
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subsignals.append(Subsignal(channel + name, Pins(width)))
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subsignals.append(Subsignal(channel + name, Pins(width)))
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