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interconnect/axi: Do not expose dest on AXI-Full (Only present for on AXI-Stream). 

We are using AXI-Stream for AXI-Full channels, so do an exception for dest signal.
This commit is contained in:
Florent Kermarrec 2022-11-08 14:51:37 +01:00
parent f617e823b9
commit b32d694ae4
2 changed files with 4 additions and 0 deletions
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2
litex/soc/interconnect/axi/axi_common.py
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@ -72,6 +72,8 @@ def connect_to_pads(bus, pads, mode="master", axi_full=False):
if channel in ["w", "r"] and axi_full: if channel in ["w", "r"] and axi_full:
sig_list += [("last", 1)] sig_list += [("last", 1)]
for name, width in sig_list: for name, width in sig_list:
if (name == "dest"):
continue # No DEST.
if (channel == "w") and (name == "id") and (bus.version == "axi4"): if (channel == "w") and (name == "id") and (bus.version == "axi4"):
continue # No WID on AXI4. continue # No WID on AXI4.
sig = getattr(ch, name) sig = getattr(ch, name)

2
litex/soc/interconnect/axi/axi_full.py
View File

@ -120,6 +120,8 @@ class AXIInterface:
channel_layout = (getattr(self, channel).description.payload_layout + channel_layout = (getattr(self, channel).description.payload_layout +
getattr(self, channel).description.param_layout) getattr(self, channel).description.param_layout)
for name, width in channel_layout: for name, width in channel_layout:
if (name == "dest"):
continue # No DEST.
if (channel == "w") and (name == "id") and (self.version == "axi4"): if (channel == "w") and (name == "id") and (self.version == "axi4"):
continue # No WID on AXI4. continue # No WID on AXI4.
subsignals.append(Subsignal(channel + name, Pins(width))) subsignals.append(Subsignal(channel + name, Pins(width)))