targets/kc705: make SDRAM controller type configurable
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d554a06eba
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b340d7ec42
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@ -83,7 +83,7 @@ class BaseSoC(SoCSDRAM):
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}
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}
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csr_map.update(SoCSDRAM.csr_map)
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csr_map.update(SoCSDRAM.csr_map)
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def __init__(self, toolchain="ise", **kwargs):
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def __init__(self, toolchain="ise", sdram_controller_type="minicon", **kwargs):
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platform = kc705.Platform(toolchain=toolchain)
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platform = kc705.Platform(toolchain=toolchain)
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SoCSDRAM.__init__(self, platform,
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SoCSDRAM.__init__(self, platform,
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clk_freq=125*1000000, cpu_reset_address=0xaf0000,
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clk_freq=125*1000000, cpu_reset_address=0xaf0000,
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@ -94,7 +94,7 @@ class BaseSoC(SoCSDRAM):
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if not self.integrated_main_ram_size:
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
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self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
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sdram_module = MT8JTF12864(self.clk_freq)
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sdram_module = MT8JTF12864(self.clk_freq)
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self.register_sdram(self.ddrphy, "lasmicon",
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self.register_sdram(self.ddrphy, sdram_controller_type,
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sdram_module.geom_settings, sdram_module.timing_settings)
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sdram_module.geom_settings, sdram_module.timing_settings)
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if not self.integrated_rom_size:
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if not self.integrated_rom_size:
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