interconnect/wishbone: fix CSRBank init

2015-11-03 18:45:23 +08:00 · 2015-11-03 18:45:23 +08:00 · d554a06eba
parent 2520ab480b
commit d554a06eba
1 changed files with 1 additions and 1 deletions
--- a/misoc/interconnect/wishbone.py
+++ b/misoc/interconnect/wishbone.py
@ -641,7 +641,7 @@ class CSRBank(csr.GenericBank):

        ###

-        GenericBank.__init__(self, description, len(self.bus.dat_w))
+        csr.GenericBank.__init__(self, description, len(self.bus.dat_w))

        for i, c in enumerate(self.simple_csrs):
            self.comb += [