mibuild: better file organization (create directory for each vendor and move programmers in it)

examples/cordic/cordic_impl.py

@@ -6,7 +6,7 @@ from migen.genlib.cordic import Cordic
 from mibuild.tools import mkdir_noerror
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx_ise import XilinxISEPlatform
+from mibuild.xilinx.ise import XilinxISEPlatform
 
 class CordicImpl(Module):
 	def __init__(self, name, **kwargs):

mibuild/altera/programmer.py

@@ -0,0 +1,10 @@
+import subprocess
+
+from mibuild.generic_programmer import GenericProgrammer
+
+class USBBlaster(GenericProgrammer):
+	needs_bitreverse = False
+
+	def load_bitstream(self, bitstream_file, port=0):
+		usb_port = "[USB-"+str(port)+"]"
+		subprocess.call(["quartus_pgm", "-m", "jtag", "-c", "USB-Blaster"+usb_port, "-o", "p;"+bitstream_file])

mibuild/generic_programmer.py

@@ -0,0 +1,30 @@
+import os
+
+class GenericProgrammer:
+	def __init__(self, flash_proxy_basename=None):
+		self.flash_proxy_basename = flash_proxy_basename
+		self.flash_proxy_dirs = [
+			"~/.migen", "/usr/local/share/migen", "/usr/share/migen",
+			"~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs"]
+
+	def set_flash_proxy_dir(self, flash_proxy_dir):
+		if flash_proxy_dir is not None:
+			self.flash_proxy_dirs = [flash_proxy_dir]
+
+	def find_flash_proxy(self):
+		for d in self.flash_proxy_dirs:
+			fulldir = os.path.abspath(os.path.expanduser(d))
+			fullname = os.path.join(fulldir, self.flash_proxy_basename)
+			if os.path.exists(fullname):
+				return fullname
+		raise OSError("Failed to find flash proxy bitstream")
+
+	# must be overloaded by specific programmer
+	def load_bitstream(self, bitstream_file):
+		raise NotImplementedError
+
+	# must be overloaded by specific programmer
+	def flash(self, address, data_file):
+		raise NotImplementedError
+
+

mibuild/platforms/apf27.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx_ise import XilinxISEPlatform
+from mibuild.xilinx.ise import XilinxISEPlatform
 
 _ios = [
 	("clk0", 0, Pins("N9"), IOStandard("LVCMOS18")),

mibuild/platforms/apf51.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx_ise import XilinxISEPlatform
+from mibuild.xilinx.ise import XilinxISEPlatform
 
 _ios = [
 	("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")),

mibuild/platforms/de0nano.py

@@ -3,8 +3,8 @@
 
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.altera_quartus import AlteraQuartusPlatform
-from mibuild.programmer import USBBlaster
+from mibuild.altera.quartus import AlteraQuartusPlatform
+from mibuild.altera.programmer import USBBlaster
 
 _io = [
 	("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")),

mibuild/platforms/kc705.py

@@ -1,9 +1,9 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
 from mibuild.xilinx_common import CRG_DS
-from mibuild.xilinx_ise import XilinxISEPlatform
-from mibuild.xilinx_vivado import XilinxVivadoPlatform
-from mibuild.programmer import XC3SProg
+from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx.vivado import XilinxVivadoPlatform
+from mibuild.xilinx.programmer import XC3SProg
 
 _io = [
 	("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),

mibuild/platforms/lx9_microboard.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx_ise import XilinxISEPlatform
+from mibuild.xilinx.ise import XilinxISEPlatform
 
 _io = [
 		("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"),

mibuild/platforms/m1.py

@@ -1,7 +1,7 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx_ise import XilinxISEPlatform
-from mibuild.programmer import UrJTAG
+from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx.programmer import UrJTAG
 
 _io = [
 	("user_led", 0, Pins("B16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),

mibuild/platforms/mixxeo.py

@@ -1,7 +1,7 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx_ise import XilinxISEPlatform
-from mibuild.programmer import UrJTAG
+from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx.programmer import UrJTAG
 
 _io = [
 	("user_led", 0, Pins("V5"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),

mibuild/platforms/ml605.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.xilinx_common import CRG_DS
-from mibuild.xilinx_ise import XilinxISEPlatform
+from mibuild.xilinx.ise import XilinxISEPlatform
 
 _io = [
 	# System clock (Differential 200MHz)

mibuild/platforms/papilio_pro.py

@@ -1,7 +1,7 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx_ise import XilinxISEPlatform
-from mibuild.programmer import XC3SProg
+from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx.programmer import XC3SProg
 
 _io = [
 	("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),

mibuild/platforms/rhino.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.xilinx_common import CRG_DS
-from mibuild.xilinx_ise import XilinxISEPlatform
+from mibuild.xilinx.ise import XilinxISEPlatform
 
 _io = [
 	("user_led", 0, Pins("Y3")),

mibuild/platforms/roach.py

@@ -1,5 +1,5 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx_ise import XilinxISEPlatform
+from mibuild.xilinx.ise import XilinxISEPlatform
 
 _io = [
 	("epb", 0,

mibuild/platforms/usrp_b100.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.xilinx_common import CRG_DS
-from mibuild.xilinx_ise import XilinxISEPlatform
+from mibuild.xilinx.ise import XilinxISEPlatform
 
 _io = [
 		("clk64", 0,

mibuild/platforms/zedboard.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx_ise import XilinxISEPlatform
+from mibuild.xilinx.ise import XilinxISEPlatform
 
 # Bank 34 and 35 voltage depend on J18 jumper setting
 _io = [

mibuild/platforms/ztex_115d.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx_ise import XilinxISEPlatform
+from mibuild.xilinx.ise import XilinxISEPlatform
 
 _io = [
 		("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")),

mibuild/xilinx/ise.py

@@ -4,7 +4,8 @@ from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
 
 from mibuild.generic_platform import *
-from mibuild import tools, xilinx_common
+from mibuild import tools
+from mibuild.xilinx import common
 
 def _format_constraint(c):
 	if isinstance(c, Pins):
@@ -92,7 +93,7 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
 		source = False
 	build_script_contents = "# Autogenerated by mibuild\nset -e\n"
 	if source:
-		settings = xilinx_common.settings(ise_path, ver, "ISE_DS")
+		settings = common.settings(ise_path, ver, "ISE_DS")
 		build_script_contents += "source " + settings + "\n"
 	if mode == "edif":
 		ext = "edif"
@@ -119,7 +120,7 @@ bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit
 	if r != 0:
 		raise OSError("Subprocess failed")
 
-class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform):
+class XilinxISEPlatform(common.XilinxGenericPlatform):
 	xst_opt = """-ifmt MIXED
 -opt_mode SPEED
 -register_balancing yes"""

mibuild/xilinx/programmer.py

@@ -1,31 +1,13 @@
 import subprocess
-import os
 
-class Programmer:
-	def __init__(self, flash_proxy_basename=None):
-		self.flash_proxy_basename = flash_proxy_basename
-		self.flash_proxy_dirs = [
-			"~/.migen", "/usr/local/share/migen", "/usr/share/migen",
-			"~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs"]
-
-	def set_flash_proxy_dir(self, flash_proxy_dir):
-		if flash_proxy_dir is not None:
-			self.flash_proxy_dirs = [flash_proxy_dir]
-
-	def find_flash_proxy(self):
-		for d in self.flash_proxy_dirs:
-			fulldir = os.path.abspath(os.path.expanduser(d))
-			fullname = os.path.join(fulldir, self.flash_proxy_basename)
-			if os.path.exists(fullname):
-				return fullname
-		raise OSError("Failed to find flash proxy bitstream")
+from mibuild.generic_programmer import GenericProgrammer
 
 def _run_urjtag(cmds):
 	with subprocess.Popen("jtag", stdin=subprocess.PIPE) as process:
 		process.stdin.write(cmds.encode("ASCII"))
 		process.communicate()
 
-class UrJTAG(Programmer):
+class UrJTAG(GenericProgrammer):
 	needs_bitreverse = True
 
 	def load_bitstream(self, bitstream_file):
@@ -49,7 +31,7 @@ flashmem "{address}" "{data_file}" noverify
 """.format(flash_proxy=flash_proxy, address=address, data_file=data_file)
 		_run_urjtag(cmds)
 
-class XC3SProg(Programmer):
+class XC3SProg(GenericProgrammer):
 	needs_bitreverse = False
 
 	def __init__(self, cable, flash_proxy_basename=None):
@@ -62,13 +44,3 @@ class XC3SProg(Programmer):
 	def flash(self, address, data_file):
 		flash_proxy = self.find_flash_proxy()
 		subprocess.call(["xc3sprog", "-v", "-c", self.cable, "-I"+flash_proxy, "{}:w:0x{:x}:BIN".format(data_file, address)])
-
-class USBBlaster(Programmer):
-	needs_bitreverse = False
-
-	def load_bitstream(self, bitstream_file, port=0):
-		usb_port = "[USB-"+str(port)+"]"
-		subprocess.call(["quartus_pgm", "-m", "jtag", "-c", "USB-Blaster"+usb_port, "-o", "p;"+bitstream_file])
-
-	def flash(self, address, data_file):
-		raise NotImplementedError

mibuild/xilinx/vivado.py

@@ -7,7 +7,8 @@ from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
 from mibuild.generic_platform import *
 
-from mibuild import tools, xilinx_common
+from mibuild import tools
+from mibuild.xilinx import common
 
 def _format_constraint(c):
 	if isinstance(c, Pins):
@@ -78,7 +79,7 @@ def _run_vivado(build_name, vivado_path, source, ver=None):
 		r = subprocess.call([build_script_file])
 	else:
 		build_script_contents = "# Autogenerated by mibuild\nset -e\n"
-		settings = xilinx_common.settings(vivado_path, ver)
+		settings = common.settings(vivado_path, ver)
 		build_script_contents += "source " + settings + "\n"
 		build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"
 		build_script_file = "build_" + build_name + ".sh"
@@ -88,9 +89,9 @@ def _run_vivado(build_name, vivado_path, source, ver=None):
 	if r != 0:
 		raise OSError("Subprocess failed")
 
-class XilinxVivadoPlatform(xilinx_common.XilinxGenericPlatform):
+class XilinxVivadoPlatform(common.XilinxGenericPlatform):
 	def __init__(self, *args, **kwargs):
-		xilinx_common.XilinxGenericPlatform.__init__(self, *args, **kwargs)
+		common.XilinxGenericPlatform.__init__(self, *args, **kwargs)
 		self.bitstream_commands = []
 		self.additional_commands = []