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soc_sdram/kcu105: add optional main_ram_size_limit and use it on KCU105 to limit to 1GB instead of 2GB. 

CSR map will need to be updated to support the 2GB.
This commit is contained in:
Florent Kermarrec 2019-11-07 09:00:54 +01:00
parent 9053d0803a
commit b52dcde9ba
2 changed files with 5 additions and 3 deletions
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4
litex/boards/targets/kcu105.py
View File

@ -96,8 +96,8 @@ class BaseSoC(SoCSDRAM):
sdram_module = EDY4016A(sys_clk_freq, "1:4") sdram_module = EDY4016A(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy, self.register_sdram(self.ddrphy,
sdram_module.geom_settings, sdram_module.geom_settings,
sdram_module.timing_settings) sdram_module.timing_settings,
main_ram_size_limit=0x40000000)
# EthernetSoC ------------------------------------------------------------------------------------------ # EthernetSoC ------------------------------------------------------------------------------------------

4
litex/soc/integration/soc_sdram.py
View File

@ -42,7 +42,7 @@ class SoCSDRAM(SoCCore):
raise FinalizeError raise FinalizeError
self._wb_sdram_ifs.append(interface) self._wb_sdram_ifs.append(interface)
def register_sdram(self, phy, geom_settings, timing_settings, **kwargs): def register_sdram(self, phy, geom_settings, timing_settings, main_ram_size_limit=None, **kwargs):
assert not self._sdram_phy assert not self._sdram_phy
self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
@ -62,6 +62,8 @@ class SoCSDRAM(SoCCore):
main_ram_size = 2**(geom_settings.bankbits + main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits + geom_settings.rowbits +
geom_settings.colbits)*phy.settings.databits//8 geom_settings.colbits)*phy.settings.databits//8
if main_ram_size_limit is not None:
main_ram_size = min(main_ram_size, main_ram_size_limit)
# SoC [<--> L2 Cache] <--> LiteDRAM ---------------------------------------------------- # SoC [<--> L2 Cache] <--> LiteDRAM ----------------------------------------------------
if self.cpu.name == "rocket": if self.cpu.name == "rocket":