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cores/jtag: Simplify/Cleanup.

This commit is contained in:
Florent Kermarrec 2022-02-01 11:32:04 +01:00
parent 1c5d91dce1
commit b59fdae588
1 changed files with 16 additions and 13 deletions
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29
litex/soc/cores/jtag.py
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@ -158,7 +158,7 @@ class JTAGTAPFSM(Module):
# Altera JTAG -------------------------------------------------------------------------------------- # Altera JTAG --------------------------------------------------------------------------------------
class AlteraJTAG(Module): class AlteraJTAG(Module):
def __init__(self, primitive, reserved_pads): def __init__(self, primitive, pads):
# Common with Xilinx. # Common with Xilinx.
self.reset = reset = Signal() # Provided by our own TAP FSM. self.reset = reset = Signal() # Provided by our own TAP FSM.
self.capture = capture = Signal() # Provided by our own TAP FSM. self.capture = capture = Signal() # Provided by our own TAP FSM.
@ -221,10 +221,10 @@ class AlteraJTAG(Module):
# connect magical reserved signals to top level pads # connect magical reserved signals to top level pads
self.comb += [ self.comb += [
rtms.eq(reserved_pads["altera_reserved_tms"]), rtms.eq(pads["altera_reserved_tms"]),
rtck.eq(reserved_pads["altera_reserved_tck"]), rtck.eq(pads["altera_reserved_tck"]),
rtdi.eq(reserved_pads["altera_reserved_tdi"]), rtdi.eq(pads["altera_reserved_tdi"]),
reserved_pads["altera_reserved_tdo"].eq(rtdo), pads["altera_reserved_tdo"].eq(rtdo),
] ]
# Connect TAP IO. # Connect TAP IO.
@ -236,12 +236,12 @@ class AlteraJTAG(Module):
self.sync.jtag_inv += tdouser.eq(tdo) self.sync.jtag_inv += tdouser.eq(tdo)
class MAX10JTAG(AlteraJTAG): class MAX10JTAG(AlteraJTAG):
def __init__(self, reserved_pads, *args, **kwargs): def __init__(self, *args, **kwargs):
AlteraJTAG.__init__(self, "fiftyfivenm_jtag", reserved_pads, *args, **kwargs) AlteraJTAG.__init__(self, "fiftyfivenm_jtag", *args, **kwargs)
class Cyclone10LPJTAG(AlteraJTAG): class Cyclone10LPJTAG(AlteraJTAG):
def __init__(self, reserved_pads, *args, **kwargs): def __init__(self, *args, **kwargs):
AlteraJTAG.__init__(self, "cyclone10lp_jtag", reserved_pads, *args, **kwargs) AlteraJTAG.__init__(self, "cyclone10lp_jtag", *args, **kwargs)
# Xilinx JTAG -------------------------------------------------------------------------------------- # Xilinx JTAG --------------------------------------------------------------------------------------
@ -370,22 +370,25 @@ class JTAGPHY(Module):
# JTAG TAP --------------------------------------------------------------------------------- # JTAG TAP ---------------------------------------------------------------------------------
if jtag is None: if jtag is None:
# Xilinx.
if device[:3] == "xc6": if device[:3] == "xc6":
jtag = S6JTAG(chain=chain) jtag = S6JTAG(chain=chain)
elif device[:3] == "xc7": elif device[:3] == "xc7":
jtag = S7JTAG(chain=chain) jtag = S7JTAG(chain=chain)
elif device[:4] in ["xcku", "xcvu"]: elif device[:4] in ["xcku", "xcvu"]:
jtag = USJTAG(chain=chain) jtag = USJTAG(chain=chain)
# Lattice.
elif device[:5] == "LFE5U": elif device[:5] == "LFE5U":
jtag = ECP5JTAG() jtag = ECP5JTAG()
# Altera/Intel.
elif device[:3].lower() in ["10m"]: elif device[:3].lower() in ["10m"]:
assert platform is not None
platform.add_reserved_jtag_decls() platform.add_reserved_jtag_decls()
jtag = MAX10JTAG(reserved_pads=platform.get_reserved_jtag_pads()) jtag = MAX10JTAG(pads=platform.get_reserved_jtag_pads())
elif device[:4].lower() in ["10cl"]: elif device[:4].lower() in ["10cl"]:
assert platform is not None
platform.add_reserved_jtag_decls() platform.add_reserved_jtag_decls()
jtag = Cyclone10LPJTAG(reserved_pads=platform.get_reserved_jtag_pads()) jtag = Cyclone10LPJTAG(pads=platform.get_reserved_jtag_pads())
else: else:
print(device) print(device)
raise NotImplementedError raise NotImplementedError