cores/jtag: Deprecate JTAG Atlantic support (Advantageously replaced by JTAG-UART).

CHANGES

@@ -32,6 +32,7 @@
 	- UART "bridge" name deprecated in favor of "crossover" (already supported).
 	- "external" CPU class support deprecated (replaced by out-of-tree support).
 	- lxterm/lxserver/lxsim short names deprecated (used long litex_xy names).
+	- Deprecate JTAG-Atlantic support (Advantageously replaced by JTAG-UART).
 
 [> 2021.12, released on January 5th 2022
 ----------------------------------------

litex/soc/cores/jtag.py

@@ -243,36 +243,6 @@ class Cyclone10LPJTAG(AlteraJTAG):
     def __init__(self, reserved_pads, *args, **kwargs):
         AlteraJTAG.__init__(self, "cyclone10lp_jtag", reserved_pads, *args, **kwargs)
 
-# Altera Atlantic JTAG -----------------------------------------------------------------------------
-
-class JTAGAtlantic(Module):
-    def __init__(self):
-        self.sink   =   sink = stream.Endpoint([("data", 8)])
-        self.source = source = stream.Endpoint([("data", 8)])
-
-        # # #
-
-        self.specials += Instance("alt_jtag_atlantic",
-            # Parameters
-            p_LOG2_RXFIFO_DEPTH       = "5", # FIXME: expose?
-            p_LOG2_TXFIFO_DEPTH       = "5", # FIXME: expose?
-            p_SLD_AUTO_INSTANCE_INDEX = "YES",
-
-            # Clk/Rst
-            i_clk   = ClockSignal("sys"),
-            i_rst_n = ~ResetSignal("sys"),
-
-            # TX
-            i_r_dat = sink.data,
-            i_r_val = sink.valid,
-            o_r_ena = sink.ready,
-
-            # RX
-            o_t_dat = source.data,
-            i_t_dav = source.ready,
-            o_t_ena = source.valid,
-        )
-
 # Xilinx JTAG --------------------------------------------------------------------------------------
 
 class XilinxJTAG(Module):

litex/soc/integration/soc.py

@@ -1166,7 +1166,6 @@ class LiteXSoC(SoC):
         supported_uarts = [
             "crossover",
             "crossover+uartbone",
-            "jtag_atlantic",
             "jtag_uart",
             "sim",
             "stub",
@@ -1199,12 +1198,6 @@ class LiteXSoC(SoC):
             self.add_uartbone(baudrate=baudrate)
             uart = UARTCrossover(**uart_kwargs)
 
-        # JTAG Atlantic.
-        elif uart_name in ["jtag_atlantic"]:
-            from litex.soc.cores.jtag import JTAGAtlantic
-            uart_phy = JTAGAtlantic()
-            uart     = UART(uart_phy, **uart_kwargs)
-
         # JTAG UART.
         elif uart_name in ["jtag_uart"]:
             from litex.soc.cores.jtag import JTAGPHY

litex/tools/litex_term.py

@@ -616,7 +616,7 @@ def _get_args():
     parser.add_argument("--base-address",   default=None,                       help="CSR base address.")
     parser.add_argument("--crossover-name", default="uart_xover",               help="Crossover UART name to use (present in design/csr.csv).")
 
-    parser.add_argument("--jtag-name",    default="jtag_uart",                help="JTAG UART type (jtag_uart or jtag_atlantic).")
+    parser.add_argument("--jtag-name",    default="jtag_uart",                help="JTAG UART type (jtag_uart).")
     parser.add_argument("--jtag-config",  default="openocd_xc7_ft2232.cfg",   help="OpenOCD JTAG configuration file for jtag_uart.")
     parser.add_argument("--jtag-chain",   default=1,                          help="JTAG chain.")
     return parser.parse_args()
@@ -634,10 +634,7 @@ def main():
         xover.open()
         port = os.ttyname(xover.name)
     elif args.port in ["jtag"]:
-        if args.jtag_name == "jtag_atlantic":
-            term.port = Nios2Terminal()
-            port = args.port
-        elif args.jtag_name == "jtag_uart":
+        if args.jtag_name == "jtag_uart":
             jtag_uart = JTAGUART(config=args.jtag_config, chain=int(args.jtag_chain))
             jtag_uart.open()
             port = os.ttyname(jtag_uart.name)