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m1crg: allow up to 150MHz pixel clock

This commit is contained in:
Sebastien Bourdeauducq 2013-03-28 20:45:42 +01:00
parent 8fd092ca12
commit b603eaf7d4
1 changed files with 1 additions and 1 deletions
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2
verilog/m1crg/m1crg.v
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@ -267,7 +267,7 @@ assign eth_tx_clk = eth_tx_clk_pad;
DCM_CLKGEN #( DCM_CLKGEN #(
.CLKFXDV_DIVIDE(2), .CLKFXDV_DIVIDE(2),
.CLKFX_DIVIDE(4), .CLKFX_DIVIDE(4),
.CLKFX_MD_MAX(2.0), .CLKFX_MD_MAX(3.0),
.CLKFX_MULTIPLY(2), .CLKFX_MULTIPLY(2),
.CLKIN_PERIOD(20.0), .CLKIN_PERIOD(20.0),
.SPREAD_SPECTRUM("NONE"), .SPREAD_SPECTRUM("NONE"),