m1crg: allow up to 150MHz pixel clock

2013-03-28 20:45:42 +01:00 · 2013-03-28 20:45:42 +01:00 · b603eaf7d4
parent 8fd092ca12
commit b603eaf7d4
1 changed files with 1 additions and 1 deletions
--- a/verilog/m1crg/m1crg.v
+++ b/verilog/m1crg/m1crg.v
@ -267,7 +267,7 @@ assign eth_tx_clk = eth_tx_clk_pad;
 DCM_CLKGEN #(
 	.CLKFXDV_DIVIDE(2),
 	.CLKFX_DIVIDE(4),
-	.CLKFX_MD_MAX(2.0),
+	.CLKFX_MD_MAX(3.0),
 	.CLKFX_MULTIPLY(2),
 	.CLKIN_PERIOD(20.0),
 	.SPREAD_SPECTRUM("NONE"),