soc/cores/spi/spi_master: Remove SPISlave.
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@ -193,94 +193,3 @@ class SPIMaster(Module, AutoCSR):
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def add_clk_divider(self):
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def add_clk_divider(self):
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self._clk_divider = CSRStorage(16, description="SPI Clk Divider.", reset=self.clk_divider.reset)
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self._clk_divider = CSRStorage(16, description="SPI Clk Divider.", reset=self.clk_divider.reset)
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self.comb += self.clk_divider.eq(self._clk_divider.storage)
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self.comb += self.clk_divider.eq(self._clk_divider.storage)
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# SPI Slave ----------------------------------------------------------------------------------------
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class SPISlave(Module):
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"""4-wire SPI Slave
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Provides a simple and minimal hardware SPI Slave with CPOL=0, CPHA=0 and build time configurable
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data_width.
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"""
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pads_layout = [("clk", 1), ("cs_n", 1), ("mosi", 1), ("miso", 1)]
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def __init__(self, pads, data_width):
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if pads is None:
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pads = Record(self.pads_layout)
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if not hasattr(pads, "cs_n"):
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pads.cs_n = Signal()
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self.pads = pads
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self.data_width = data_width
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self.start = Signal() # o, Signal a start of SPI Xfer.
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self.length = Signal(8) # o, Signal the length of the SPI Xfer (in bits).
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self.done = Signal() # o, Signal that SPI Xfer is done/inactive.
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self.irq = Signal() # o, Signal the end of a SPI Xfer.
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self.mosi = Signal(data_width) # i, Data to send on SPI MOSI.
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self.miso = Signal(data_width) # o, Data received on SPI MISO.
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self.loopback = Signal() # i, Loopback enable.
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# # #
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clk = Signal()
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cs = Signal()
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mosi = Signal()
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miso = Signal()
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# IOs <--> Internal (input resynchronization) ----------------------------------------------
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self.specials += [
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MultiReg(pads.clk, clk),
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MultiReg(~pads.cs_n, cs),
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MultiReg(pads.mosi, mosi),
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]
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self.comb += pads.miso.eq(miso)
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# Clock detection --------------------------------------------------------------------------
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clk_d = Signal()
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clk_rise = Signal()
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clk_fall = Signal()
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self.sync += clk_d.eq(clk)
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self.comb += clk_rise.eq(clk & ~clk_d)
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self.comb += clk_fall.eq(~clk & clk_d)
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# Control FSM ------------------------------------------------------------------------------
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(cs,
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self.start.eq(1),
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NextValue(self.length, 0),
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NextState("XFER")
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).Else(
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self.done.eq(1)
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)
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)
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fsm.act("XFER",
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If(~cs,
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self.irq.eq(1),
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NextState("IDLE")
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),
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NextValue(self.length, self.length + clk_rise)
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)
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# Master In Slave Out (MISO) generation (generated on spi_clk falling edge) ----------------
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miso_data = Signal(data_width)
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self.sync += [
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If(self.start,
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miso_data.eq(self.miso)
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).Elif(cs & clk_fall,
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miso_data.eq(Cat(Signal(), miso_data[:-1]))
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)
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]
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self.comb += [
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If(self.loopback,
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miso.eq(mosi)
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).Else(
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miso.eq(miso_data[-1]),
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)
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]
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# Master Out Slave In (MOSI) capture (captured on spi_clk rising edge) ---------------------
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self.sync += [
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If(cs & clk_rise,
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self.mosi.eq(Cat(mosi, self.mosi[:-1]))
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)
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]
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