soc: fix unit-tests
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@ -1,5 +1,3 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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@ -710,8 +708,8 @@ class SoC(Module):
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slaves = bus_slaves,
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register = True,
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timeout_cycles = self.bus.timeout)
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if hasattr(self, "ctrl") and self.bus.timeout is not None:
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self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
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if hasattr(self, "ctrl") and self.bus.timeout is not None:
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self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
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# SoC CSR Interconnect ---------------------------------------------------------------------
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self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
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@ -111,6 +111,8 @@ class SoCCore(SoC):
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self.integrated_sram_size = integrated_sram_size
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self.integrated_main_ram_size = integrated_main_ram_size
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self.csr_data_width = csr_data_width
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self.with_wishbone = with_wishbone
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self.wishbone_timeout_cycles = wishbone_timeout_cycles
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