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integration/soc/add_adapter: Add AXI2AXILite and AXI2Wishbone support.

This commit is contained in:
Florent Kermarrec 2022-06-15 19:37:04 +02:00
parent da5d9ecf9b
commit b6f4302e8e
1 changed files with 5 additions and 2 deletions
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7
litex/soc/integration/soc.py
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@ -314,8 +314,9 @@ class SoCBusHandler(Module):
if interface.data_width != self.data_width: if interface.data_width != self.data_width:
interface_cls = type(interface) interface_cls = type(interface)
converter_cls = { converter_cls = {
wishbone.Interface: wishbone.Converter, wishbone.Interface : wishbone.Converter,
axi.AXILiteInterface: axi.AXILiteConverter, axi.AXILiteInterface : axi.AXILiteConverter,
axi.AXIInterface : axi.AXIConverter,
}[interface_cls] }[interface_cls]
converted_interface = interface_cls(data_width=self.data_width) converted_interface = interface_cls(data_width=self.data_width)
if direction == "m2s": if direction == "m2s":
@ -346,6 +347,8 @@ class SoCBusHandler(Module):
(axi.AXILiteInterface, wishbone.Interface) : axi.AXILite2Wishbone, (axi.AXILiteInterface, wishbone.Interface) : axi.AXILite2Wishbone,
(wishbone.Interface , axi.AXIInterface) : axi.Wishbone2AXI, (wishbone.Interface , axi.AXIInterface) : axi.Wishbone2AXI,
(axi.AXILiteInterface, axi.AXIInterface) : axi.AXILite2AXI, (axi.AXILiteInterface, axi.AXIInterface) : axi.AXILite2AXI,
(axi.AXIInterface, axi.AXILiteInterface): axi.AXI2AXILite,
(axi.AXIInterface, wishbone.Interface) : axi.AXI2Wishbone,
}[type(master), type(slave)] }[type(master), type(slave)]
bridge = bridge_cls(master, slave) bridge = bridge_cls(master, slave)
self.submodules += bridge self.submodules += bridge