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gowin: add hack for copackaged PSRAM 

Some Gowin FPGAs has copackaged "PSRAM" instead of "HyperRAM". They're
in fact also HyperRAM, but named differently and because of this needs
slightly changed hack.

Add hack for PSRAM too. In case of two PSRAM chips are used, the bus is
wider so the needed definition is already in place, so the bus width
hack is not needed.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
This commit is contained in:
Icenowy Zheng 2022-01-23 02:30:18 +08:00
parent bcc9c14c7e
commit b7b054d48e
1 changed files with 2 additions and 0 deletions
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2
litex/build/gowin/gowin.py
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@ -109,6 +109,8 @@ class GowinToolchain:
# Apply Synthesis directives. # Apply Synthesis directives.
tools.replace_in_file(v_file, "wire [0:0] IO_hpram_rwds,", "wire [0:0] IO_hpram_rwds, /* synthesis syn_tristate = 1 */") tools.replace_in_file(v_file, "wire [0:0] IO_hpram_rwds,", "wire [0:0] IO_hpram_rwds, /* synthesis syn_tristate = 1 */")
tools.replace_in_file(v_file, "wire [7:0] IO_hpram_dq,", "wire [7:0] IO_hpram_dq, /* synthesis syn_tristate = 1 */") tools.replace_in_file(v_file, "wire [7:0] IO_hpram_dq,", "wire [7:0] IO_hpram_dq, /* synthesis syn_tristate = 1 */")
tools.replace_in_file(v_file, "[1:0] IO_psram_rwds,", "[1:0] IO_psram_rwds, /* synthesis syn_tristate = 1 */")
tools.replace_in_file(v_file, "[15:0] IO_psram_dq,", "[15:0] IO_psram_dq, /* synthesis syn_tristate = 1 */")
def build(self, platform, fragment, def build(self, platform, fragment,
build_dir = "build", build_dir = "build",