cores/cpu: Fix automatic collection for Rocket/BlackParrot/EOS-S3.

This commit is contained in:
Florent Kermarrec 2022-01-20 17:44:35 +01:00
parent a76828a40a
commit bcc9c14c7e
5 changed files with 9 additions and 10 deletions

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@ -94,11 +94,10 @@ def collect_cpus():
continue
# OK, it seems to be a CPU; now get the class and add it to dict.
cpu = file
cpu_module = f"{cpu}"
cpu = file
sys.path.append(path)
for cpu_name, cpu_cls in inspect.getmembers(importlib.import_module(cpu_module), inspect.isclass):
if cpu.replace("_", "") == cpu_name.lower():
for cpu_name, cpu_cls in inspect.getmembers(importlib.import_module(cpu), inspect.isclass):
if cpu_name.lower() in [cpu, cpu.replace("_", "")]:
cpus[cpu] = cpu_cls
# Return collected CPUs.

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@ -1 +1 @@
from litex.soc.cores.cpu.blackparrot.core import BlackParrotRV64
from litex.soc.cores.cpu.blackparrot.core import BlackParrot

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@ -52,9 +52,9 @@ GCC_FLAGS = {
"sim": "-march=rv64imafd -mabi=lp64d ",
}
# BlackParrotRV64 ----------------------------------------------------------------------------------
# BlackParrot --------------------------------------------------------------------------------------
class BlackParrotRV64(CPU):
class BlackParrot(CPU):
family = "riscv"
name = "blackparrot"
human_name = "BlackParrotRV64[imafd]"

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@ -1 +1 @@
from litex.soc.cores.cpu.rocket.core import RocketRV64
from litex.soc.cores.cpu.rocket.core import Rocket

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@ -86,9 +86,9 @@ CPU_SIZE_PARAMS = {
"full4q": ( 256, 64, 4),
}
# Rocket RV64 --------------------------------------------------------------------------------------
# Rocket ------------------------------------------------------------------------------------------
class RocketRV64(CPU):
class Rocket(CPU):
family = "riscv"
name = "rocket"
human_name = "RocketRV64[imac]"