build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC"

2018-03-12 09:33:05 +01:00 · 2018-03-12 09:33:05 +01:00 · b7f7c8d159
parent 4324c6f666
commit b7f7c8d159
1 changed files with 1 additions and 1 deletions
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@ -134,7 +134,7 @@ xilinx_special_overrides = {
 class XilinxDDROutputImplS6(Module):
    def __init__(self, i1, i2, o, clk):
        self.specials += Instance("ODDR2",
-                p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="SYNC",
+                p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC",
                i_C0=clk, i_C1=~clk, i_CE=1, i_S=0, i_R=0,
                i_D0=i1, i_D1=i2, o_Q=o,
        )