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gen/fhdl/verilog: allow single element verilog inline attribute

This commit is contained in:
Florent Kermarrec 2019-08-28 05:15:45 +02:00
parent 5a7b4c3406
commit b845755995
2 changed files with 8 additions and 11 deletions
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2
litex/build/lattice/diamond.py
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@ -10,8 +10,6 @@ import shutil
from migen.fhdl.structure import _Fragment from migen.fhdl.structure import _Fragment
from litex.gen.fhdl.verilog import DummyAttrTranslate
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build import tools from litex.build import tools
from litex.build.lattice import common from litex.build.lattice import common

17
litex/gen/fhdl/verilog.py
View File

@ -198,11 +198,13 @@ def _printattr(attr, attr_translate):
firsta = True firsta = True
for attr in sorted(attr, for attr in sorted(attr,
key=lambda x: ("", x) if isinstance(x, str) else x): key=lambda x: ("", x) if isinstance(x, str) else x):
if isinstance(attr, tuple):
# platform-dependent attribute # platform-dependent attribute
if isinstance(attr, tuple):
attr_name, attr_value = attr attr_name, attr_value = attr
else: elif attr not in attr_translate.keys():
attr_name, attr_value = attr, None
# translated attribute # translated attribute
else:
at = attr_translate[attr] at = attr_translate[attr]
if at is None: if at is None:
continue continue
@ -210,7 +212,9 @@ def _printattr(attr, attr_translate):
if not firsta: if not firsta:
r += ", " r += ", "
firsta = False firsta = False
r += attr_name + " = \"" + attr_value + "\"" r += attr_name
if attr_value is not None:
r += " = \"" + attr_value + "\""
if r: if r:
r = "(* " + r + " *)" r = "(* " + r + " *)"
return r return r
@ -366,14 +370,9 @@ def _printspecials(overrides, specials, ns, add_data_file, attr_translate):
return r return r
class DummyAttrTranslate:
def __getitem__(self, k):
return (k, "true")
def convert(f, ios=None, name="top", def convert(f, ios=None, name="top",
special_overrides=dict(), special_overrides=dict(),
attr_translate=DummyAttrTranslate(), attr_translate={},
create_clock_domains=True, create_clock_domains=True,
display_run=False, display_run=False,
reg_initialization=True, reg_initialization=True,