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soc/cores/i2c: fix CSR generation

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Richard Tucker 2023-02-10 12:49:57 +11:00 committed by Andrew Dennison
parent 90128756f9
commit b8b6ecef7c
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/i2c.py
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@ -177,7 +177,7 @@ class I2CMasterMachine(Module):
# ("stop", 1),
# ("idle", 1),
# ])
class I2CMaster(Module):
class I2CMaster(Module, AutoCSR):
def __init__(self, pads, bus=None):
if bus is None:
bus = wishbone.Interface(data_width=32)