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soc/cores/sdram/phy: fix S6QuarterRateDDRPHY

This commit is contained in:
Florent Kermarrec 2016-03-29 14:59:30 +02:00
parent 7cd83c420f
commit b8d89535fd
1 changed files with 2 additions and 1 deletions
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3
litex/soc/cores/sdram/phy/s6ddrphy.py
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@ -21,6 +21,7 @@ from operator import or_
from litex.gen import * from litex.gen import *
from litex.gen.genlib.record import * from litex.gen.genlib.record import *
from litex.gen.fhdl.decorators import ClockDomainsRenamer
from litex.soc.interconnect.dfi import * from litex.soc.interconnect.dfi import *
from litex.soc.cores.sdram import settings as sdram_settings from litex.soc.cores.sdram import settings as sdram_settings
@ -399,7 +400,7 @@ class S6HalfRateDDRPHY(Module):
class S6QuarterRateDDRPHY(Module): class S6QuarterRateDDRPHY(Module):
def __init__(self, pads, rd_bitslip, wr_bitslip, dqs_ddr_alignment): def __init__(self, pads, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
half_rate_phy = S6HalfRateDDRPHY(pads, "DDR3", rd_bitslip, wr_bitslip, dqs_ddr_alignment) half_rate_phy = S6HalfRateDDRPHY(pads, "DDR3", rd_bitslip, wr_bitslip, dqs_ddr_alignment)
self.submodules += RenameClockDomains(half_rate_phy, {"sys" : "sys2x"}) self.submodules += ClockDomainsRenamer("sys2x")(half_rate_phy)
addressbits = len(pads.a) addressbits = len(pads.a)
bankbits = len(pads.ba) bankbits = len(pads.ba)