interconnect/axi: Simplify/Fix IOs generation. (Param signals were missing for AXIFull).

litex/soc/interconnect/axi/axi_full.py

@@ -100,9 +100,14 @@ class AXIInterface:
     def get_ios(self, bus_name="wb"):
         subsignals = []
         for channel in ["aw", "w", "b", "ar", "r"]:
+            # Control Signals.
             for name in ["valid", "ready"] + (["last"] if channel in ["w", "r"] else []):
                 subsignals.append(Subsignal(channel + name, Pins(1)))
-            for name, width in getattr(self, channel).description.payload_layout:
+
+            # Payload/Params Signals.
+            channel_layout = (getattr(self, channel).description.payload_layout +
+                              getattr(self, channel).description.param_layout)
+            for name, width in channel_layout:
                 subsignals.append(Subsignal(channel + name, Pins(width)))
         ios = [(bus_name , 0) + tuple(subsignals)]
         return ios

litex/soc/interconnect/axi/axi_stream.py

@@ -48,14 +48,10 @@ class AXIStreamInterface(stream.Endpoint):
             Subsignal("tready", Pins(1)),
         ]
 
-        # Payload Signals.
-        subsignals += [Subsignal("tdata", Pins(len(self.data)))]
-        subsignals += [Subsignal("tkeep", Pins(len(self.keep)))]
-
-        # Param Signals.
-        subsignals += [Subsignal("tid",   Pins(len(self.id)))]
-        subsignals += [Subsignal("tdest", Pins(len(self.dest)))]
-        subsignals += [Subsignal("tuser", Pins(len(self.user)))]
+        # Payload/Params Signals.
+        channel_layout = (self.description.payload_layout + self.description.param_layout)
+        for name, width in channel_layout:
+            subsignals.append(Subsignal(f"t{name}", Pins(width)))
         ios = [(bus_name , 0) + tuple(subsignals)]
         return ios