Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Clean up

This commit is contained in:
Florent Kermarrec 2012-09-09 20:51:15 +02:00
parent 2092c5a138
commit b8eaf0906a
2 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
migScope/tools/vcd.py
View File

@ -1,5 +1,7 @@
import sys
import datetime
sys.path.append("../../")
from migScope.tools.conv import *
class Var:
@ -161,7 +163,7 @@ def main():
myvcd.add(Var("wire",3,"foo3"))
myvcd.add(Var("wire",4,"foo4"))
ramp = [i%128 for i in range(1024)]
myvcd.add(Var("wire",16,"sinus",ramp))
myvcd.add(Var("wire",16,"ramp",ramp))
print(myvcd)
if __name__ == '__main__':

6
sim/tb_Migscope.py
View File

@ -9,7 +9,6 @@ import sys
sys.path.append("../")
from migScope import trigger, recorder
from migScope.tools.truthtable import *
from migScope.tools.vcd import *
@ -76,11 +75,14 @@ def csr_transactions(trigger0, recorder0):
#Arm
yield TWrite(recorder0.address + 1, 1)
# Wait Record to be done
##############################
global rec_done
while not rec_done:
yield None
# Read recorded data
##############################
global dat_rdy
for t in range(64):
yield TWrite(recorder0.address + 7, 1)