Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
Build your hardware, easily!
24 Commits 40 Branches 14 Tags 26 MiB
C 52.8%
Python 43.5%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
Other 0.6%
Go to file
Florent Kermarrec b8eaf0906a Clean up 2012-09-09 20:51:15 +02:00
migScope Clean up 2012-09-09 20:51:15 +02:00
sim Clean up 2012-09-09 20:51:15 +02:00
spi2Csr tb_spi2Csr: Add clk_ratio 2012-08-26 13:03:11 +02:00
README new library spi2Csr (skeleton) 2012-08-13 01:02:38 +02:00
top.py split migScope to trigger & recorder 2012-08-26 21:30:23 +02:00

README 

[> migScope
------------

This is a small Logic Analyser to be embedded in a Fpga design to debug internal
or external signals.

[> Status:
Early development phase

[> Contact
E-mail: florent@enjoy-digital.fr