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Merge pull request #595 from betrusted-io/master 

wire up missing register bits.
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enjoy-digital 2020-07-20 22:47:16 +02:00 committed by GitHub
parent 87d7f6e72e 53a567daef
commit b92519502a
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litex/soc/cores/i2s.py
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@ -283,10 +283,12 @@ class S7I2S(Module, AutoCSR, AutoDoc):
o_WRERR = rx_wrerr, o_WRERR = rx_wrerr,
) )
self.comb += [ # Wire up the status signals and interrupts self.comb += [ # Wire up the status signals and interrupts
self.rx_stat.fields.overflow.eq(rx_wrerr),
self.rx_stat.fields.underflow.eq(rx_rderr), self.rx_stat.fields.underflow.eq(rx_rderr),
self.rx_stat.fields.dataready.eq(rx_almostfull), self.rx_stat.fields.dataready.eq(rx_almostfull),
self.rx_stat.fields.wrcount.eq(rx_wrcount), self.rx_stat.fields.wrcount.eq(rx_wrcount),
self.rx_stat.fields.rdcount.eq(rx_rdcount), self.rx_stat.fields.rdcount.eq(rx_rdcount),
self.rx_stat.fields.empty.eq(rx_empty),
self.ev.rx_ready.trigger.eq(rx_almostfull), self.ev.rx_ready.trigger.eq(rx_almostfull),
self.ev.rx_error.trigger.eq(rx_wrerr | rx_rderr), self.ev.rx_error.trigger.eq(rx_wrerr | rx_rderr),
] ]