Merge pull request #595 from betrusted-io/master
wire up missing register bits.
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commit
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@ -283,10 +283,12 @@ class S7I2S(Module, AutoCSR, AutoDoc):
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o_WRERR = rx_wrerr,
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)
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self.comb += [ # Wire up the status signals and interrupts
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self.rx_stat.fields.overflow.eq(rx_wrerr),
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self.rx_stat.fields.underflow.eq(rx_rderr),
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self.rx_stat.fields.dataready.eq(rx_almostfull),
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self.rx_stat.fields.wrcount.eq(rx_wrcount),
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self.rx_stat.fields.rdcount.eq(rx_rdcount),
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self.rx_stat.fields.empty.eq(rx_empty),
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self.ev.rx_ready.trigger.eq(rx_almostfull),
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self.ev.rx_error.trigger.eq(rx_wrerr | rx_rderr),
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]
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