build: Remove osfpga skeleton (would need feedbacks & updates).
This commit is contained in:
Florent Kermarrec
parent
351a583f1c
commit
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from litex.build.osfpga.platform import OSFPGAPlatform
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen.fhdl.module import Module
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import *
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# OS-FPGA AsyncResetSynchronizer -------------------------------------------------------------------
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class OSFPGAAsyncResetSynchronizerImpl(Module):
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def __init__(self, cd, async_reset):
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self.comb += cd.rst.eq(async_reset) # FIXME: Implement.
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class OSFPGAAsyncResetSynchronizer:
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@staticmethod
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def lower(dr):
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return OSFPGAAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
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# OS-FPGA Special Overrides -------------------------------------------------------------------------
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osfpga_special_overrides = {
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AsyncResetSynchronizer: OSFPGAAsyncResetSynchronizer,
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}
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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import math
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import subprocess
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from shutil import which, copyfile
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from migen.fhdl.structure import _Fragment
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from litex.build.generic_toolchain import GenericToolchain
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from litex.build.generic_platform import *
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from litex.build import tools
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# OSFPGAToolchain ----------------------------------------------------------------------------------
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class OSFPGAToolchain(GenericToolchain):
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attr_translate = {}
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def __init__(self, toolchain):
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super().__init__()
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self.toolchain = toolchain
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self.clocks = dict()
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# Constraints ----------------------------------------------------------------------------------
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def build_io_constraints(self):
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return ("", "") # TODO
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# Timing Constraints (.sdc) --------------------------------------------------------------------
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def build_timing_constraints(self, vns):
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sdc = []
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for clk, [period, name] in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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clk_sig = self._vns.get_name(clk)
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if name is None:
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name = clk_sig
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sdc.append(f"create_clock -name {name} -period {str(period)} [get_ports {{{clk_sig}}}]")
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with open(f"{self._build_name}.sdc", "w") as f:
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f.write("\n".join(sdc))
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return (self._build_name + ".sdc", "SDC")
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# Project --------------------------------------------------------------------------------------
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def build_project(self):
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tcl = []
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# Create Design.
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tcl.append(f"create_design {self._build_name}")
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# Set Device.
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tcl.append(f"target_device {self.platform.device.upper()}")
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# Add Include Path.
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tcl.append("add_include_path ./")
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for include_path in self.platform.verilog_include_paths:
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tcl.append(f"add_include_path {include_path}")
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# Add Sources.
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for f, typ, lib in self.platform.sources:
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tcl.append(f"add_design_file {f}")
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# Set Top Module.
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tcl.append(f"set_top_module {self._build_name}")
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# Add Timings Constraints.
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tcl.append(f"add_constraint_file {self._build_name}.sdc")
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# Run.
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tcl.append("synth")
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tcl.append("packing")
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tcl.append("place")
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tcl.append("route")
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tcl.append("sta")
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tcl.append("power")
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tcl.append("bitstream")
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# Generate .tcl.
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with open("build.tcl", "w") as f:
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f.write("\n".join(tcl))
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# Script ---------------------------------------------------------------------------------------
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def build_script(self):
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return "" # unused
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def run_script(self, script):
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toolchain_sh = self.toolchain
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if which(toolchain_sh) is None:
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msg = f"Unable to find {toolchain_sh.upper()} toolchain, please:\n"
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msg += f"- Add {toolchain_sh.upper()} toolchain to your $PATH."
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raise OSError(msg)
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if subprocess.call([toolchain_sh, "--batch", "--script", "build.tcl"]) != 0:
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raise OSError(f"Error occured during {toolchain_sh.upper()}'s script execution.")
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from litex.build.generic_platform import GenericPlatform
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from litex.build.osfpga import common, osfpga
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# OSFPGAPlatform -----------------------------------------------------------------------------------
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class OSFPGAPlatform(GenericPlatform):
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_bitstream_ext = ".bin"
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_supported_toolchains = ["osfpga"]
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def __init__(self, device, *args, toolchain="foedag", devicename=None, **kwargs):
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GenericPlatform.__init__(self, device, *args, **kwargs)
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self.devicename = devicename
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if toolchain in ["foedag", "raptor"]:
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self.toolchain = osfpga.OSFPGAToolchain(toolchain=toolchain)
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else:
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raise ValueError(f"Unknown toolchain {toolchain}")
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = dict(common.osfpga_special_overrides)
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args,
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special_overrides = so,
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attr_translate = self.toolchain.attr_translate,
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**kwargs)
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def build(self, *args, **kwargs):
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return self.toolchain.build(self, *args, **kwargs)
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def add_false_path_constraint(self, from_, to):
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pass # FIXME: Implement.
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#!/usr/bin/env python3
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.build.generic_platform import Pins
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from litex.build.osfpga import OSFPGAPlatform
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# Minimal Platform ---------------------------------------------------------------------------------
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_io = [
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("clk", 0, Pins(1)),
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("led", 0, Pins(1))
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]
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class Platform(OSFPGAPlatform):
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def __init__(self):
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OSFPGAPlatform.__init__(self, device="gemini", toolchain="raptor", io=_io)
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# Minimal Design -----------------------------------------------------------------------------------
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platform = Platform()
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clk = platform.request("clk")
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led = platform.request("led")
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module = Module()
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module.clock_domains.cd_sys = ClockDomain("sys")
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module.comb += module.cd_sys.clk.eq(clk)
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counter = Signal(26)
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module.comb += led.eq(counter[25])
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module.sync += counter.eq(counter + 1)
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# Build --------------------------------------------------------------------------------------------
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platform.build(module, build_name="blinky", run=True)
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#!/usr/bin/env python3
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.io import CRG
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from litex.build.generic_platform import Pins, Subsignal
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from litex.build.osfpga import OSFPGAPlatform
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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# Platform ---------------------------------------------------------------------------------
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_io = [
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# Clk.
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("clk", 0, Pins(1)),
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# Serial.
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("serial", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1)),
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),
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]
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class Platform(OSFPGAPlatform):
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def __init__(self, toolchain="raptor", device="gemini"):
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OSFPGAPlatform.__init__(self, device=device, toolchain=toolchain, io=_io)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, platform, sys_clk_freq=int(10e6), **kwargs):
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("clk"))
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX Test SoC on OS-FPGA", **kwargs)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX Test SoC on OS-FPGA")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--toolchain", default="raptor", help="FPGA toolchain.")
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target_group.add_argument("--device", default="gemini", help="FPGA device.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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platform = Platform(toolchain=args.toolchain, device=args.device)
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soc = BaseSoC(platform,**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build()
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if __name__ == "__main__":
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main()
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