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uart: Enable buffering the FIFO. 

On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
This commit is contained in:
Tim 'mithro' Ansell 2018-10-27 16:02:53 -07:00
parent f916705313
commit ba0dd5728e
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/uart.py
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@ -157,7 +157,7 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
fifo = stream.AsyncFIFO([("data", 8)], depth) fifo = stream.AsyncFIFO([("data", 8)], depth)
return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo) return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
else: else:
return stream.SyncFIFO([("data", 8)], depth) return stream.SyncFIFO([("data", 8)], depth, buffered=True)
class UART(Module, AutoCSR): class UART(Module, AutoCSR):