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Merge branch 'master' of github.com:m-labs/misoc

This commit is contained in:
Sebastien Bourdeauducq 2015-04-02 10:14:24 +08:00
parent 2900429e65 60124be293
commit bbdbf87599
6 changed files with 18 additions and 10 deletions
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4
misoclib/com/liteeth/example_designs/make.py
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@ -72,6 +72,8 @@ if __name__ == "__main__":
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs) soc = top_class(platform, **top_kwargs)
soc.finalize() soc.finalize()
memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()
# decode actions # decode actions
action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"] action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
@ -121,7 +123,7 @@ System Clk: {} MHz
subprocess.call(["rm", "-rf", "build/*"]) subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]: if actions["build-csr-csv"]:
csr_csv = cpuif.get_csr_csv(soc.csr_regions) csr_csv = cpuif.get_csr_csv(csr_regions)
write_to_file(args.csr_csv, csr_csv) write_to_file(args.csr_csv, csr_csv)
if actions["build-bitstream"]: if actions["build-bitstream"]:

7
misoclib/com/liteeth/example_designs/targets/base.py
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@ -23,14 +23,15 @@ class BaseSoC(SoC, AutoCSR):
mac_address=0x10e2d5000000, mac_address=0x10e2d5000000,
ip_address="192.168.0.42"): ip_address="192.168.0.42"):
clk_freq = int((1/(platform.default_clk_period))*1000000000) clk_freq = int((1/(platform.default_clk_period))*1000000000)
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200) SoC.__init__(self, platform, clk_freq,
SoC.__init__(self, platform, clk_freq, self.uart2wb, cpu_type="none",
with_cpu=False,
with_csr=True, csr_data_width=32, with_csr=True, csr_data_width=32,
with_uart=False, with_uart=False,
with_identifier=True, with_identifier=True,
with_timer=False with_timer=False
) )
self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# wishbone SRAM (to test Wishbone over UART and Etherbone) # wishbone SRAM (to test Wishbone over UART and Etherbone)

4
misoclib/mem/litesata/example_designs/make.py
View File

@ -69,6 +69,8 @@ if __name__ == "__main__":
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs) soc = top_class(platform, **top_kwargs)
soc.finalize() soc.finalize()
memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()
# decode actions # decode actions
action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"] action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
@ -124,7 +126,7 @@ BIST: {}
subprocess.call(["rm", "-rf", "build/*"]) subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]: if actions["build-csr-csv"]:
csr_csv = cpuif.get_csr_csv(soc.get_csr_regions()) csr_csv = cpuif.get_csr_csv(csr_regions)
write_to_file(args.csr_csv, csr_csv) write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]: if actions["build-core"]:

2
misoclib/soc/sdram.py
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@ -78,7 +78,7 @@ class SDRAMSoC(SoC):
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width)) raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
def do_finalize(self): def do_finalize(self):
if not self.integrated_ram_size: if not self.integrated_main_ram_size:
if not self._sdram_phy_registered: if not self._sdram_phy_registered:
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()") raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
SoC.do_finalize(self) SoC.do_finalize(self)

4
misoclib/tools/litescope/example_designs/make.py
View File

@ -72,6 +72,8 @@ if __name__ == "__main__":
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs) soc = top_class(platform, **top_kwargs)
soc.finalize() soc.finalize()
memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()
# decode actions # decode actions
action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"] action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
@ -130,7 +132,7 @@ RLE: {}
subprocess.call(["rm", "-rf", "build/*"]) subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]: if actions["build-csr-csv"]:
csr_csv = cpuif.get_csr_csv(soc.csr_regions) csr_csv = cpuif.get_csr_csv(csr_regions)
write_to_file(args.csr_csv, csr_csv) write_to_file(args.csr_csv, csr_csv)
if actions["build-bitstream"]: if actions["build-bitstream"]:

7
misoclib/tools/litescope/example_designs/targets/simple.py
View File

@ -16,14 +16,15 @@ class LiteScopeSoC(SoC, AutoCSR):
csr_map.update(SoC.csr_map) csr_map.update(SoC.csr_map)
def __init__(self, platform): def __init__(self, platform):
clk_freq = int((1/(platform.default_clk_period))*1000000000) clk_freq = int((1/(platform.default_clk_period))*1000000000)
self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200) SoC.__init__(self, platform, clk_freq,
SoC.__init__(self, platform, clk_freq, self.uart2wb, cpu_type="none",
with_cpu=False,
with_csr=True, csr_data_width=32, with_csr=True, csr_data_width=32,
with_uart=False, with_uart=False,
with_identifier=True, with_identifier=True,
with_timer=False with_timer=False
) )
self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.io = LiteScopeIO(8) self.submodules.io = LiteScopeIO(8)