litex_sim: Switch to soc_core_args/soc_core_argdict.
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@ -19,7 +19,6 @@ from litex.build.sim.config import SimConfig
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from litex.soc.integration.common import *
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from litex.soc.integration.common import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.soc import *
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from litex.soc.integration.soc import *
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from litex.soc.cores.bitbang import *
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from litex.soc.cores.bitbang import *
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@ -369,7 +368,7 @@ def generate_gtkw_savefile(builder, vns, trace_fst):
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def sim_args(parser):
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def sim_args(parser):
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builder_args(parser)
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builder_args(parser)
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soc_sdram_args(parser)
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soc_core_args(parser)
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parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
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parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
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parser.add_argument("--rom-init", default=None, help="rom_init file")
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parser.add_argument("--rom-init", default=None, help="rom_init file")
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parser.add_argument("--ram-init", default=None, help="ram_init file")
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parser.add_argument("--ram-init", default=None, help="ram_init file")
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@ -399,7 +398,7 @@ def main():
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sim_args(parser)
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sim_args(parser)
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args = parser.parse_args()
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args = parser.parse_args()
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soc_kwargs = soc_sdram_argdict(args)
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soc_kwargs = soc_core_argdict(args)
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builder_kwargs = builder_argdict(args)
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builder_kwargs = builder_argdict(args)
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sys_clk_freq = int(1e6)
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sys_clk_freq = int(1e6)
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