cores/cpu: Fix automatic collection for Rocket/BlackParrot/EOS-S3.
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@ -94,11 +94,10 @@ def collect_cpus():
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continue
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continue
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# OK, it seems to be a CPU; now get the class and add it to dict.
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# OK, it seems to be a CPU; now get the class and add it to dict.
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cpu = file
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cpu = file
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cpu_module = f"{cpu}"
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sys.path.append(path)
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sys.path.append(path)
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for cpu_name, cpu_cls in inspect.getmembers(importlib.import_module(cpu_module), inspect.isclass):
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for cpu_name, cpu_cls in inspect.getmembers(importlib.import_module(cpu), inspect.isclass):
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if cpu.replace("_", "") == cpu_name.lower():
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if cpu_name.lower() in [cpu, cpu.replace("_", "")]:
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cpus[cpu] = cpu_cls
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cpus[cpu] = cpu_cls
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# Return collected CPUs.
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# Return collected CPUs.
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@ -1 +1 @@
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from litex.soc.cores.cpu.blackparrot.core import BlackParrotRV64
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from litex.soc.cores.cpu.blackparrot.core import BlackParrot
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@ -52,9 +52,9 @@ GCC_FLAGS = {
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"sim": "-march=rv64imafd -mabi=lp64d ",
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"sim": "-march=rv64imafd -mabi=lp64d ",
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}
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}
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# BlackParrotRV64 ----------------------------------------------------------------------------------
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# BlackParrot --------------------------------------------------------------------------------------
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class BlackParrotRV64(CPU):
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class BlackParrot(CPU):
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family = "riscv"
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family = "riscv"
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name = "blackparrot"
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name = "blackparrot"
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human_name = "BlackParrotRV64[imafd]"
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human_name = "BlackParrotRV64[imafd]"
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@ -1 +1 @@
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from litex.soc.cores.cpu.rocket.core import RocketRV64
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from litex.soc.cores.cpu.rocket.core import Rocket
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@ -86,9 +86,9 @@ CPU_SIZE_PARAMS = {
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"full4q": ( 256, 64, 4),
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"full4q": ( 256, 64, 4),
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}
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}
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# Rocket RV64 --------------------------------------------------------------------------------------
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# Rocket ------------------------------------------------------------------------------------------
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class RocketRV64(CPU):
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class Rocket(CPU):
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family = "riscv"
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family = "riscv"
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name = "rocket"
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name = "rocket"
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human_name = "RocketRV64[imac]"
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human_name = "RocketRV64[imac]"
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