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Merge pull request #742 from rprinz08/master 

Enable etherbone usage on multiple ethernet interfaces
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enjoy-digital 2020-12-23 10:44:40 +01:00 committed by GitHub
parent 1a338b602a c99c96bc68
commit bddb170650
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1 changed files with 4 additions and 2 deletions
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litex/soc/integration/soc.py
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@ -1362,7 +1362,7 @@ class LiteXSoC(SoC):
eth_tx_clk) eth_tx_clk)
# Add Etherbone -------------------------------------------------------------------------------- # Add Etherbone --------------------------------------------------------------------------------
def add_etherbone(self, name="etherbone", phy=None, def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth",
mac_address = 0x10e2d5000000, mac_address = 0x10e2d5000000,
ip_address = "192.168.1.50", ip_address = "192.168.1.50",
udp_port = 1234, udp_port = 1234,
@ -1377,7 +1377,9 @@ class LiteXSoC(SoC):
mac_address = mac_address, mac_address = mac_address,
ip_address = ip_address, ip_address = ip_address,
clk_freq = self.clk_freq) clk_freq = self.clk_freq)
ethcore = ClockDomainsRenamer("eth_tx")(ethcore) ethcore = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx"})(ethcore)
self.submodules.ethcore = ethcore self.submodules.ethcore = ethcore
# Clock domain renaming # Clock domain renaming