Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Enable etherbone usage on multiple ethernet interfaces

This commit is contained in:
rprinz08 2020-12-22 21:13:10 +01:00
parent 1a338b602a
commit c99c96bc68
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litex/soc/integration/soc.py
View File

@ -1362,7 +1362,7 @@ class LiteXSoC(SoC):
eth_tx_clk)
# Add Etherbone --------------------------------------------------------------------------------
def add_etherbone(self, name="etherbone", phy=None,
def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth",
mac_address = 0x10e2d5000000,
ip_address = "192.168.1.50",
udp_port = 1234,
@ -1377,7 +1377,9 @@ class LiteXSoC(SoC):
mac_address = mac_address,
ip_address = ip_address,
clk_freq = self.clk_freq)
ethcore = ClockDomainsRenamer("eth_tx")(ethcore)
ethcore = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx"})(ethcore)
self.submodules.ethcore = ethcore
# Clock domain renaming